Tomohiro Hamajima

Evaluation of depth profile of defects in ultrathin Si film on buried SiO2 formed by implanted oxygen

A simple technique is presented for evaluating defect profiles in ultrathin Si films on buried SiO2 formed by implanted oxygen. A combination of thinning by sacrificial oxidation and epitaxial film growth by UHV‐CVD is used. By measuring the defect density of the epitaxial film with respect to the thickness prior to epitaxial growth, the profile of the initial defect density can easily be evaluated. This technique is applied to evaluate the Si on insulator structure fabricated by state‐of‐the‐art technique, in which low dose oxygen implantation (∼4×1017 cm−2) and high temperature internal oxidation processes are used. The defect density at the surface of the film is 250 cm−2. However, as the buried interface is approached, the defect density increases. The defect density at 20 nm from the buried interface is as high as 6×105 cm−2. A defect generation mechanism is also discussed.

An intelligent power device using poly-Si sandwiched wafer bonding technique

A new simple isolation structure has been realized by using poly-Si sandwiched wafer bonding technique. We confirmed that the poly-Si layer enabled the bonded interface to be void-free and electrically perfect, and had the effect that it enabled the reverse recovery time of the parasitic diode of Vertical DMOSFET (VDMOS) to be short. In the new structure, the isolation capabilities were adequate to integrate 60 V VDMOS and control circuits on the same chip. Especially, the parasitic bipolar action has been suppressed. We evaluated an intelligent power device which uses this technique and have confirmed the availability of the new isolation structure.

New SOI structures for intelligent power ICs with vertical double-diffused MOS output devices

Intelligent power ICs with vertical double-diffused MOS (VDMOS) output devices are used for solenoid controlled applications. Many structures have been proposed for these power ICs. We have developed poly-Si sandwiched bonded (PSB) structures which use a Sb doped poly-Si and crystal-Si bonding technique. However these PSB structures have a high fabrication cost, because the fabrication process includes Sb diffusion into poly-Si layers. In this paper, we first propose an improved fabrication process of PSB structures without Sb diffusion into poly-Si layers. Second, we propose a new SOI structure with gaps fabricated by a wafer direct bonding technique. Both structures enable us to obtain low-cost intelligent power ICs with VDMOS.

Application of partially bonded SOI structure to an intelligent power device having vertical DMOSFET

In recent years, many types of Intelligent Power Devices (IPDs) have been developed. A key technology of developing the IPDs is the isolation between power device and control circuit. The isolation structures and its manufacturing methods are required to be more efficient and cost effective. We had been developed a low side switch IPD having Vertical DMOSFET (VDMOS) output by using poly-crystalline silicon sandwiched wafer bonding (PSB) technique. In this PSB structure, it is easy to achieve void-free bonding because the extremely flat poly-crystalline silicon (poly-Si) layer surface and the single-crystalline silicon (Si) substrate surface are bonded together. However, the PSB structure is still expensive. To reduce the fabrication cost, we have made a study of the direct bonding without poly-Si and proposed a new SOI structure named partially bonded (PB) structure. This paper reports the evaluation results that we applied the PB structure to a low side switch IPD for the first time.

Void-Free Bonded SOI Substrates for High-Voltage, High-Current Vertical DMOS-Type Power ICs

New isolated structures for intelligent power ICs were developed using a wafer bonding technique. These structures have partial buried oxide films for dielectric isolation and buried poly-Si layers for wafer bonding. In this bonding technique, bonding surfaces are a poly-Si layer and a crystalline silicon surface; this combination of bonding surfaces leads to void-free bonding. The electrical perfection of the vertical output device in the new structure was obtained by diffusing antimony into the poly-Si layer. These results indicate that intelligent power ICs can be manufactured by using the new structure.