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Featured researches published by Ketan Zaveri.


custom integrated circuits conference | 1999

A next generation architecture optimized for high density system level integration

Richard G. Cliff; Srinivas T. Reddy; Cameron San Jose McClintock; David Jefferson; Chris Lane; Ketan Zaveri; Manuel Mejia; Andy L. Lee; Ninh D. Ngo; R. Altaf; Bruce B. Pedersen; Francis B. Heile; James Schleicher; John E. Turner

Altera has developed a next generation architecture called APEX/sup TM/ to improve overall logic efficiency, performance and provide a framework to add a much broader range of features which enables complete system level integration of a users system. This new architecture will support a family of devices exceeding 2 million gates in density. Density and speed improvements are achieved through an enhanced hierarchical routing structure.


Archive | 2002

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

Ketan Zaveri; Christopher F. Lane; Srinivas T. Reddy; Andy L. Lee; Cameron McClintock; Bruce B. Pedersen


Archive | 1998

Programmable logic device circuitry for improving multiplier speed and/or efficiency

Christopher F. Lane; Srinivas T. Reddy; Richard G. Cliff; Ketan Zaveri; Bruce B. Pedersen; Kerry Veenstra


Archive | 2003

Programmable logic device with hierarchical interconnection resources

Srinivas T. Reddy; Richard G. Cliff; Christopher F. Lane; Ketan Zaveri; Manuel Mejia; David Jefferson; Bruce B. Pedersen; Andy L. Lee


Archive | 2001

Configurable memory structures in a programmable logic device

Andy L. Lee; Christopher F. Lane; Srinivas T. Reddy; Brian D. Johnson; Ketan Zaveri; Mario Guzman; Quyen Doan


Archive | 2004

Redundancy structures and methods in a programmable logic device

Michael Chan; Paul Leventis; David Lewis; Ketan Zaveri; Hyun Yi; Chris Lane


Archive | 1998

Programmable logic array integrated circuit with distributed random access memory array

Ketan Zaveri; Richard G. Cliff; Srinivas T. Reddy


Archive | 2005

Method and system for reducing static leakage current in programmable logic devices

Ketan Zaveri; Christopher F. Lane


Archive | 2000

Multifunction memory array in a programmable logic device

Srinivas T. Reddy; Brian D. Johnson; Christopher F. Lane; Ketan Zaveri


Archive | 2013

Techniques for providing clock signals in an integrated circuit

Ramanand Venkata; Ryan Fung; Ketan Zaveri

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