Kevin C. Brown

A complementary bipolar technology family with a Vertically Integrated PNP for high-frequency analog applications

Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP/sup TMI/) which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies.

A 170 volt polysilicon-emitter complementary bipolar IC technology with full dielectric isolation

A high-speed, high-voltage polysilicon-emitter complementary bipolar IC process is described. Process features include >170 V NPN and PNP BV/sub ceo/, dielectric isolation using a bonded wafer substrate and deep trenches, polysilicon resistors, polysilicon to metal capacitors, and a two-level metal back end.

Development and production integration of a planarized AlCu interconnect process for submicron CMOS

A planarized aluminum alloy interconnect has been developed as an alternative to tungsten plugs for a 0.65 (mu) CMOS technology. Contact resistance can increase with either an inadequate RF sputter clean or titanium that is too thin to reduce the native oxide. Diffusion barrier results show that a minimum amount of titanium nitride, whether deposited conventionally or with collimation, is necessary for low junction leakage and good sort yield. Stacked contacts and vias are supported while via resistance and defect density are improved. Electrical bridging due to silicon residues from AlSiCu can be minimized with metal overetching, but not to the extent of AlCu. Sidewall pitting was observed to be due to galvanic corrosion from copper precipitate formation. Overall yield has been improved along with decreased wafer cost compared to conventional tungsten plug technology.

Issues associated with submicron via formation

The relationship between plasma etch chemistry and via resistance has been investigated. A gas mixture of Ar/CF4/CHF3 yields lower via resistance than Ar/CF4. However, decreasing the overetch of the Ar/CF4 process improves resistance and failure rate. A longer DI water rinse after solvent strip improves via resistance and failure rate by either dissolution of aluminum fluoride, or corrosion of the aluminum under the via lifting out the organometallic polymer. Higher deep UV photostabilization temperature before etch gives a lower via failure rate with tighter distributions. XPS results show that the Ar/CF4 gas chemistry increases sputtering of aluminum out of the vias during overetch, increasing the amount of aluminum fluoride present, which correlates with the worsened via resistance observed.