Wipawan Yindeepol

Precision electrical trimming of very low TCR poly-SiGe resistors

Precision electrical trimming of stacked Si/SiGe polycrystalline resistors available from the extrinsic base structure of a SiGe BiCMOS technology has been demonstrated for the first time. It is shown that pulse current trimming techniques can be used to trim the poly-SiGe resistors by up to 50% from their original values with accuracy better than /spl plusmn/0.5%. The temperature coefficient of resistance (TCR) is shown to be linearly proportional to the percent change in electrically trimmed poly-SiGe resistance. Finally, we demonstrate resistance cycling using an electrical trim/recovery sequence, indicating that the technique is reversible and is governed by dopant segregation/diffusion mechanisms. The results are consistent with those obtained on conventional polysilicon resistors suggesting that the introduction of a strained SiGe layer does not adversely affect the electrical trim properties of these resistors.

A complementary bipolar technology family with a Vertically Integrated PNP for high-frequency analog applications

Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP/sup TMI/) which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies.

CBC8: A 0.25 µm SiGe-CBiCMOS technology platform on thick-film SOI for high-performance analog and RF IC design

A production released complementary-SiGe BiCMOS technology on SOI has been developed for high speed analog and RFIC applications. It features matched SiGe:C PNP and NPN transistors. The PNP shows cutting edge performance metrics with β·VA =17,000 and near record fT·BVCEO ≥ 195GHz·V for a 5V process while demonstrating best in class linearity on a fully differential amplifier design. A modular process flow was leveraged to enhance the Analog design needs for the platform. For higher-speed lower power, we also demonstrate a low voltage SiGe NPN with peak fT of 50 GHz at low-bias (VCE = 0.5V), ideal for load line drive. Finally, we discuss core CMOS devices which utilize a dual-gate oxide process for improved mixed-signal mixed-voltage design and better optimization of digital blocks.

Back-gated buried oxide MOSFETs in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2/spl times/10/sup 12//cm/sup 2/ at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4/spl times/10/sup 10//cm/sup 2/ in the buried oxide.

A 170 volt polysilicon-emitter complementary bipolar IC technology with full dielectric isolation

A high-speed, high-voltage polysilicon-emitter complementary bipolar IC process is described. Process features include >170 V NPN and PNP BV/sub ceo/, dielectric isolation using a bonded wafer substrate and deep trenches, polysilicon resistors, polysilicon to metal capacitors, and a two-level metal back end.

Impact of buried layer processing on gate oxide integrity [CMOS processing]

Buried layers are used in bipolar devices to lower collector resistance in bulk silicon and SOI (silicon-on-insulator) technologies. They are also used with deep trench for isolating different devices types. This work investigates the effect of buried layer processing on CMOS capacitor reliability, comparing results between bulk silicon and SOI substrates. Opposing results from bulk and SOI technologies indicate different degradation mechanisms at play. The SOI starting material requires that metal contaminant gettering be taken in to account in the processing of the buried layers.

Physical modeling and alleviation of shallow-trench-isolation charging effects in silicon-on-insulator complementary bipolar technology

Oxide charging, adversely influencing PNP collector-base capacitance, has been observed and modeled physically in a complementary bipolar process that uses dielectric isolation. A practical solution to alleviate this effect is described along with trade-offs involved in process and device design.