Kevin J. Yang

MOS capacitance measurements for high-leakage thin dielectrics

As oxide thickness is reduced below 2.5 nm in MOS devices, both series and shunt parasitic resistances become significant in capacitance-voltage (C-V) measurements. A new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies. This technique is demonstrated for a 1.7 nm SiO/sub 2/ capacitor.

Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices

An analytic model of the direct tunneling current in metal–oxide–semiconductor devices as a function of oxide field is presented. Accurate modeling of the low-field roll-off in the current results from proper modeling of the field dependencies of the sheet charge, electron impact frequency on the interface, and tunneling probability. To obtain the latter dependence, a modified WKB approximation is used.

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs

The impact of energy quantization on gate tunneling current is studied for double-gate and ultrathin body MOSFETs. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage by as much as an order of magnitude. The effects of body thickness scaling and channel crystallographic orientation are studied. The impact of threshold voltage control solutions, including doped channel and asymmetric double-gate structures is also investigated. Future gate dielectric thickness scaling and the use of high-/spl kappa/ gate dielectrics are discussed.

Quantum effect in oxide thickness determination from capacitance measurement

Simple quantitative models of charge displacement due to the quantum effect and its influence on gate oxide thickness measurements are presented. An effective oxide thickness (T/sub DC/) is introduced which is relevant to MOSFET current modeling. Physical oxide thickness and T/sub DC/ can be extracted easily from capacitance measurement, and the electrical thickness can be predicted from a target physical thickness using these new models.

Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs

The impact of energy quantization on gate tunneling current is studied for double-gate and ultra-thin body MOSFETs. The lower vertical electric field in the channel of these thin-body devices causes a reduction in gate leakage by as much as an order of magnitude. The additional effects of channel doping and high-k dielectrics are also investigated.

Two silicon nitride technologies for post-SiO 2 MOSFET gate dielectric

P-MOSFETs with 14 /spl Aring/ equivalent oxide thickness (EOT) were fabricated using both JVD Si/sub 3/N/sub 4/ and RTCVD Si/sub 3/N/sub 4//SiO/sub x/N/sub y/ gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO/sub 2/ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large.

Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics

Abstract Effective electron mobility has been studied in MOSFETs with ultrathin silicon nitride/oxynitride stacked gate dielectrics formed by rapid thermal chemical vapor deposition. The mobility in these devices is degraded compared to those with SiO 2 (the universal mobility curve). Quantitative analysis suggests that the degradation is due to coulombic scattering from both bulk charges in the dielectric and interface trapped charges. Finally, after investigating the impact of process parameters on mobility, it is concluded that interfacial oxynitride grown at higher pressure in nitric oxide is advantageous for achieving thinner effective stack thicknesses and for preserving electron mobility.

Frequency Dependence of Capacitance Measurement for Advanced Gate Dielectrics

1. Introduction Capacitance-voltage (C-V) measurements are a fundamental characterization technique for MOS devices. However, as the oxide thickness is reduced and gate dielectrics comprised of stacks of novel materials are employed, CV measurement and analysis are made more complex by the frequency-dependence of the measured capacitance. This paper presents an analysis of the sources of the frequency-dependence with guidelines for interpreting frequency-dependent capacitance data.

Improved MOSFET electron mobility model for advanced gate dielectric stacks

The scaling of CMOS technology requires continued reduction in the capacitance equivalent thickness (CET) of the gate dielectric. Since scaling of pure Si02 to thicknesses less than 12 .& becomes problematic due to the increased tunneling current, it is necessary to incorporate a material with a higher dielectric constant into the gate stack. Integration of `true high-K¿ dielectrics, such as ZrO] or HQ, into a CMOS process flow still remains a major challenge. In contrast, an oxynitride/Si3N4 gate dielectric stack has been demonstrated in high-performance MOSFETs with the thinnest CET (7A) reported to date [I]. Therefore, Si3N4 and oxynitrides will likely be the most important gate dielectric aterials during this decade. Although alternative gate dielectrics suppress gate leakage current, they can degrade carrier channel mobility. In this work, we propose a quantitative model for electron mobility in MOSFETs with oxynitride/Si,N, gate dielectric. We also show that electron mobility is directly related to the nitrogen content in the dielectric film and to the fabrication conditions.