Matt Hankinson

Run-to-run critical dimension and sidewall angle lithography control using the PROLITH simulator

We derive and investigate three different run-to-run (R2R) feedback controllers for the purpose of trying to minimize the detrimental effects of lithography process disturbances on critical resist profiles. Our controllers manipulate the dose and focus inputs and include Kalman filtering schemes that estimate the disturbances. The first controller adjusts the critical dimension (CD) and sidewall angle (SWA) of the resist profile. The second controller compensates for the print bias between isolated and dense lines. The third controller finds the best tradeoff between CD, SWA, and print bias. We tested the performance of the controllers using the lithography simulator PROLITH (v.7.0). The results showed a reduction of the effect of the disturbances on the CD, SWA, and print bias. Moreover, the results quantify the benefit of using focus, in addition to dose, as a control input for the purpose of controlling the resist profile.

Correlating scatterometry to CD-SEM and electrical gate measurements at the 90-nm node using TMU analysis

Currently, CD-SEMs are the tool of choice for in-line gate length measurements for most semiconductor manufacturers. This is in large part due to their flexibility, throughput, and ability to correlate well to physical measurements (e.g., XSEM). However, scatterometry is being used by an increasing number of manufacturers to monitor and control gate lengths. But can a scatterometer measure such small critical dimensions well enough? This paper explores this question by analyzing data taken from wafers processed using 90 nm node technology. These wafers were measured after gate formation (gate final CD) using a CD-SEM as well as a scatterometer. They were then processed into the back-end-of-line and measured electrically. This electrical measurement, called Lpoly, is an important parametric device measurement and is used to screen product before it reaches final electrical test. It is therefore critical for the in-line metrology immediately after gate formation to have excellent correlation to Lpoly. Analysis shows that the scatterometer correlates well to both in-line CD-SEM measurements across multiple structures as well as electrical Lpoly measurements. More importantly, the scatterometer is shown to be approximately equivalent to the CD-SEM when both are correlated to Lpoly. Since several scatterometry targets with different pitches were measured, the amount of correlation as a function of pitch is also investigated. Because traditional methods of correlation, such as Ordinary Least Squares (OLS), have severe limitations, Total Measurement Uncertainty (TMU) analysis is used as a highly effective assessment methodology. This paper also shows how TMU analysis is used to improve the scatterometry model and understand the relative contributions from obstacles that hinder the achievement of even better correlations.

Critical dimension control of a plasma etch process by integrating feedforward and feedback run-to-run control

In this article, we have derived a run-to-run (R2R) control design technique that integrates feedforward and feedback control on the etch process. The purpose is to minimize the effect of an oxygen flow disturbance during the resist trim on the polysilicon critical dimension (CD) after the main etch. The R2R controller manipulates the resist trim time based on feedforward measurements of the resist CD at the end of the lithography and feedback measurements from polysilicon CD at the end of the etch process. The purpose of the feedforward measurement is to adjust the resist trim time using a model of the relation between trim time, resist CD before the resist trim and polysilicon CD after the main etch. The purpose of the feedback measurement is to adjust this model to compensate for the oxygen flow disturbance during the resist trim. The resulting controller is called feedforward/feedback (FF/FB) controller. The FF/FB controller is tested using simulations and experiments conducted on an etch tool manufactured by Lam Research. The simulations and experimental results show that the FF/FB controller attenuates linear drift and shift in the polysilicon CD caused by the oxygen flow disturbance. Moreover, the results quantify the significant benefit of integrating feedforward and feedback control in addition to only using a feedforward control in minimizing the polysilicon CD deviations from the etch target.

Spectroscopic CD technology for gate process control

Spectroscopic CD (SCD) technology provides high precision shape information with excellent correlation to established critical dimension metrology. Poly-gate wafers from over 20 lots produced in a high-volume manufacturing fab were measured and analyzed with KLA-Tencors SCD and SEM CD tools. APC simulations on the SCD data demonstrate the potential to reduce the CD deviation from the process target. Focus-exposure process window analysis using additional shape information available with SCD shows the potential value of the more complete view for lithographic cluster tool monitoring.

Advanced Process Control of overlay with optimal sampling

This paper evaluates sampling plans for overlay metrology in the context of Advanced Process Control (APC). The relationship between APC opportunity (the maximum benefit achievable via APC) and correctable accuracy is investigated. The tradeoff between spatial and temporal sampling density is considered as well. This tradeoff expresses the relationship between temporal sampling needed to realize APC benefit and spatial sampling needed to achieve a level of total overlay error. We find that the spatial sampling plan impacts both the proportion of process disturbance in the measured variability and the frequency distribution of the disturbance. As a result of a smaller magnitude and lower frequency disturbance in the10-field plan, APC performance with this plan is substantially better than with the 4-field plan. Over a realistic range of temporal sampling, APC of correctables derived from the 10-field sample plan result in a 20 to 25 percent improvement over the baseline of no control on 4-field based correctables. When APC is applied to 4-field correctables, only about 8 to 10 percent improvement is achieved.

Yield loss in lithographic patterning at the 65nm node and beyond

Parametric yield loss is an increasing fraction of total yield loss. Much of this originates in lithography in the form of pattern-limited yield. In particular, the ITRS has identified CD control at the 65nm technology node as a potential roadblock with no known solutions. At 65nm, shrinking design rules and narrowing process windows will become serious yield limiters. In high-volume production, corrections based on lot averages will have diminished correlation to device yield because APC systems will dramatically reduce error at the lot and wafer levels. As a result, cross-wafer and cross-field errors will dominate the systematic variation on 300mm wafers. Much of the yield loss will arise from hidden systematic variation, including intra-wafer dose and focus errors that occur during lithographic exposure. In addition, corollary systematic variation in the profiles of critical high-aspect-ratio structures will drive requirements for vertical process control. In this work, we model some of the potential yield losses and show how sensitive focus-exposure monitors and spectroscopic ellipsometry can be used to reduce the impact of hidden error on pattern limited yield, adding tens of millions of dollars in additional revenue per factory per year.

Microeconomics of advanced process window control for 50-nm gates

Fundamentally, advanced process control enables accelerated design-rule reduction, but simple microeconomic models that directly link the effects of advanced process control to profitability are rare or non-existent. In this work, we derive these links using a simplified model for the rate of profit generated by the semiconductor manufacturing process. We use it to explain why and how microprocessor manufacturers strive to avoid commoditization by producing only the number of dies required to satisfy the time-varying demand in each performance segment. This strategy is realized using the tactic known as speed binning, the deliberate creation of an unnatural distribution of microprocessor performance that varies according to market demand. We show that the ability of APC to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process window variation.

Microeconomics of accelerated shrinks in demand-limited markets

Previously, we developed a simple microeconomic model that directly links metrology, yield, and profitability. The model has been used to explain the effect of metrology on gross margins in 200 mm and 300 mm factories. The same model can be adapted to evaluate the relative economic impact of accelerated design-rule shrinks in demand-limited markets. Using examples relevant to the high-volume production of memory products, we demonstrate that metrology-driven shrinks are still the most cost-effective way to improve profitability. We also describe the means by which these shrinks can be achieved in high-volume factories.

Metrology needs and challenges for the semiconductor industry

The aggressively shrinking process window drives the semiconductor manufacturer to examine, refine, and control all aspects of the manufacturing process. Process budgets leave little room for error contribution. Budget management, and ultimately achieving the goal, requires an understanding of the constituent components, and development of mitigation strategies. We present some of the challenges facing our industry and strategies that we are taking to address them.

Understanding the impact of full-field mask error factor

Deep-UV lithography using 248 and 193-nm light will be the microlithography technology of choice for the manufacturing of advanced memory and logic semiconductor devices for the next decade. Since 193nm lithography development has been slow, the extension of 248nm technology to 0.150micrometers and beyond has accelerated. Advanced techniques, such as Optical Proximity Correction and phase shift masks will be needed in order to maintain sufficient process latitude. This continuous reduction of k1 to near ½ wavelength has intensified and issues related to MEF have become a concern. MEF, a phenomenon first discussed by Maurer et al., is define as the CD Error at wafer level divided by the CD Error at reticle level multiplied by the lens magnification. There have been numerous publications discussing the im pact of MEF on CD budgets for line space and contact imaging. This paper will discuss recent work to investigate full field MEF, the impact on choice of illumination conditions and how photoresist can significantly influence MEF. Data based on simulation and experiment was collected with high numerical aperture 248 nm imaging using binary reticles with conventional illumination.