Ady Levy

Implementation of spectroscopic critical dimension (SCD) (TM) for gate CD control and stepper characterization

Smaller device dimensions and tighter process control windows have created a need for CD metrology tools having higher levels of precision and accuracy. Furthermore, the need to detect and measure changes in feature profiles is becoming critical to in-line process control and stepper evaluation for sub-0.18micrometers technology. Spectroscopic CD (SCDTM) is an optical metrology technique that can address these needs. This work describes the use of a spectroscopic CD metrology tool to measure and characterize the focus and exposure windows for the process. The results include comparison to the established in-line CD-SEM, as well as a cross-section SEM. Repeatability and long-term stability data form a gate level nominal process are also presented.

Advanced process control for poly-Si gate etching using integrated CD metrology

Advanced integrated metrology capability is actively being pursued in several process areas, including etch, to shorten process cycle times, enable wafer-level advanced process control (APC), and improve productivity. In this study, KLA-Tencors scatterometry-based iSpectra Spectroscopic CD was integrated on a Lam 2300 Versys Star silicon etch system. Feed-forward control techniques were used to reduce critical dimension (CD) variation. Pre-etch CD measurements were sent to the etch system to modify the trim time and achieve targeted CDs. CDs were brought to within 1 nm from a starting CD spread of 25 nm, showing the effectiveness of this process control approach together with the advantages of spectroscopic CD metrology over conventional CD measurement techniques.

Spectroscopic CD metrology for sub-100-nm lithography process control

The accelerating trend to smaller linewidths and low-k1 lithography makes metrology and process control more challenging with each succeeding technology generation. Optical CD metrology based on spectroscopic ellipsometry provides higher precision, improved matching, and richer information for line width and shape (profile) control which complement conventional litho metrology techniques. Analysis of site-to-site, within-field, field-to-field, and cross-wafer CD and line-shape distributions using KLA-Tencor SpectraCD permits separation of sources of variation between the stepper and track thus enabling proper process control. Focus-exposure analysis using SpectraCD data provides a more complete understanding of the lithography process window. Comparison between SpectraCD CD measurements on nominal 1:5 Line/Space ratio grating targets to isolated line CD-SEM measurements show excellent correlation over a large focus-exposure process range, including sub-100nm features. This result provides verification that SCD measurements on grating targets can be used to monitor and provide feedback to lithography process for isolated lines.

Spectroscopic CD technology for gate process control

Spectroscopic CD (SCD) technology provides high precision shape information with excellent correlation to established critical dimension metrology. Poly-gate wafers from over 20 lots produced in a high-volume manufacturing fab were measured and analyzed with KLA-Tencors SCD and SEM CD tools. APC simulations on the SCD data demonstrate the potential to reduce the CD deviation from the process target. Focus-exposure process window analysis using additional shape information available with SCD shows the potential value of the more complete view for lithographic cluster tool monitoring.

Lithography aware overlay metrology target design method

We present a metrology target design (MTD) framework based on co-optimizing lithography and metrology performance. The overlay metrology performance is strongly related to the target design and optimizing the target under different process variations in a high NA optical lithography tool and measurement conditions in a metrology tool becomes critical for sub-20nm nodes. The lithography performance can be quantified by device matching and printability metrics, while accuracy and precision metrics are used to quantify the metrology performance. Based on using these metrics, we demonstrate how the optimized target can improve target printability while maintaining the good metrology performance for rotated dipole illumination used for printing a sub-100nm diagonal feature in a memory active layer. The remaining challenges and the existing tradeoff between metrology and lithography performance are explored with the metrology target designer’s perspective. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.

Metrology target design (MTD) solution for diagonally orientated DRAM layer

We present a novel metrology target design framework using the scanner exit pupil wavefront analysis together with Zernike sensitivity analysis (ZSA) based on the Monte-Carlo technique. The proposed method enables the design of robust metrology targets that maximize target process window (PW) while minimizing placement error discrepancies with device features in the presence of spatial and temporal variation of the aberration characteristics of an exposure tool. Knowing the limitations of lithography systems, design constraints, and detailed lithography information including illumination, mask type, etc., we can successfully design an optimal metrology target. We have validated our new metrology target design (MTD) method for one of the challenging DRAM active layer consisting of diagonal line and space patterns illuminated by a rotated extreme dipole source. We find that an optimal MTD target gives the maximized PW and the strong device correlation, resulting in the dramatic improvement of overall overlay performance. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.

Highly sensitive focus monitoring technique based on illumination and target co-optimization

We present a cost-effective focus monitoring technique based on the illumination and the target co-optimization. An advanced immersion scanner can provide the freeform illumination that enables the use of any kind of custom source shape by using a programmable array of thousands of individually adjustable micro-mirrors. Therefore, one can produce non-telecentricity using the asymmetric illumination in the scanner with the optimized focus target on the cost-effective binary OMOG mask. Then, the scanner focus variations directly translate into easily measurable overlay shifts in the printed pattern with high sensitivity (ΔShift/Δfocus = 60nm/100nm). In addition, the capability of using the freeform illumination allows us to computationally co-optimize the source and the focus target, simultaneously, generating not only vertical or horizontal shifts, but also introducing diagonal pattern shifts. The focus-induced pattern shifts can be accurately measured by standard wafer metrology tools such as CD-SEM and overlay metrology tools.

Quantifying imaging performance bounds of extreme dipole illumination in high NA optical lithography

We present a framework to analyze the performance of optical imaging in a hyper numerical aperture (NA) immersion lithography scanner. We investigate the method to quantify imaging performance by computing upperand lower-bounds on the threshold normalized image log-slope (NILS) and the depth of focus (DOF) in conjunction with the traditional image quality metrics such as the mask error enhancement factor (MEEF) and the linearity for various different pitches and line to space (LS) duty cycles. The effects of the interaction between the light illumination and the feature size are extensively characterized based on the aerial image (AI) behavior in particular for the extreme dipole illumination that is one of the commonly used off-axis illuminations for sub-100nm logic and memory devices, providing resolution near the physical limit of an optical single patterning step. The proposed aerial imaging-based DOF bounds are compared to the results obtained from an experimentally calibrated resist model, and we observed good agreement. In general, the extreme dipole illumination is only optimal for a single particular pitch, therefore understanding the through-pitch imaging performance bound, which depends on the illumination shape, pattern size, and process conditions, is critically important. We find that overall imaging performance varies depending upon the number of diffracted beams passing through the scanner optics. An even number of beams provides very different trends compared to the results from an odd-number of beams. This significant non-linear behavior occurs in certain pitch regions corresponding to 3 beam interference imaging. In this region the imaging performance and the pattern printability become extremely sensitive to the LS duty cycle. In addition, there is a notable tradeoff between the DOF and the NILS that is observed in the problematic 3-beam region and this tradeoff eventually affects the achievable process window (PW). Given the practical real world constraints such as the design rules and target design restrictions, computing upper- and lower-bounds of the through-pitch DOF and NILS will be especially useful for both lithographers and metrology target designers in understanding this complex behavior, as well as helping in the design of optimal targets used for applications including alignment, overlay control, and process control in high volume semiconductor manufacturing.

High order overlay modeling and APC simulation with Zernike-Legendre polynomials

Feedback control of overlay errors to the scanner is a well-established technique in semiconductor manufacturing [1]. Typically, overlay errors are measured, and then modeled by least-squares fitting to an overlay model. Overlay models are typically Cartesian polynomial functions of position within the wafer (Xw, Yw), and of position within the field (Xf, Yf). The coefficients from the data fit can then be fed back to the scanner to reduce overlay errors in future wafer exposures, usually via a historically weighted moving average. In this study, rather than using the standard Cartesian formulation, we examine overlay models using Zernike polynomials to represent the wafer-level terms, and Legendre polynomials to represent the field-level terms. Zernike and Legendre polynomials can be selected to have the same fitting capability as standard polynomials (e.g., second order in X and Y, or third order in X and Y). However, Zernike polynomials have the additional property of being orthogonal over the unit disk, which makes them appropriate for the wafer-level model, and Legendre polynomials are orthogonal over the unit square, which makes them appropriate for the field-level model. We show several benefits of Zernike/Legendre-based models in this investigation in an Advanced Process Control (APC) simulation using highly-sampled fab data. First, the orthogonality property leads to less interaction between the terms, which makes the lot-to-lot variation in the fitted coefficients smaller than when standard polynomials are used. Second, the fitting process itself is less coupled – fitting to a lower-order model, and then fitting the residuals to a higher order model gives very similar results as fitting all of the terms at once. This property makes fitting techniques such as dual pass or cascading [2] unnecessary, and greatly simplifies the options available for the model recipe. The Zernike/Legendre basis gives overlay performance (mean plus 3 sigma of the residuals) that is the same as standard Cartesian polynomials, but with stability similar to the dual-pass recipe. Finally, we show that these properties are intimately tied to the sample plan on the wafer, and that the model type and sampling must be considered at the same time to demonstrate the benefits of an orthogonal set of functions.

Microeconomics of advanced process window control for 50-nm gates

Fundamentally, advanced process control enables accelerated design-rule reduction, but simple microeconomic models that directly link the effects of advanced process control to profitability are rare or non-existent. In this work, we derive these links using a simplified model for the rate of profit generated by the semiconductor manufacturing process. We use it to explain why and how microprocessor manufacturers strive to avoid commoditization by producing only the number of dies required to satisfy the time-varying demand in each performance segment. This strategy is realized using the tactic known as speed binning, the deliberate creation of an unnatural distribution of microprocessor performance that varies according to market demand. We show that the ability of APC to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process window variation.