Kevin S. Petrarca

3D copper TSV integration, testing and reliability

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

Through silicon via (TSV) effects on devices in close proximity - the role of mobile ion penetration - characterization and mitigation

A new interaction between TSV processes and devices in close proximity, different from mechanical stress, is identified, studied and mitigated. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. An improved process is presented and confirmed in test structures and DRAM.

System-in-package for extreme environments

The moon and Mars are extreme environments for electronics in terms of both low temperatures and wide temperature extremes. A system-in-package (SiP) approach has been chosen to build electronics capable of operating in these extreme environments without the need for warm electronics boxes to maintain an earth-like environment. The SiP is based on thin film copper/polyimide substrate technology with embedded passive components. Both wire bond and flip chip assembly are being used. The assembly is hermetically packaged in an alumina package.

Selective nickel and gold plating for enhanced wire bonding technology

Nickel and gold are electrodeposited on wire bond pads by a newly developed selective plating process in which plating is done without photoresist. The gold terminal metal offers exciting advantage over the traditional aluminum metallurgy. The unique self-encapsulating structure of gold and nickel over copper seed is illustrated. The plating tool, process control and thickness uniformity are described. We have evaluated this structure with probing, aging and stress under high temperature (200degC) in conjunction with bonding. We also varied the bonding conditions to allow a wider choice of inter-level dielectrics and structure/device placement under pads. All the data shows that this is a viable alternative to the current process of record