Kevin W. Kark

Storage hierarchy to support a 600 MHz G5 S/390 microprocessor

Although a microprocessors maximum frequency and internal design are important, the storage hierarchy is the primary reason for the large system performance improvement of the S/390 G5 compared to the G4. The improvement is achieved with an L2 cache, system controller and memory interface clocked at 1/4 the microprocessor frequency.

Advancing reliability, availability, and serviceability with the IBM z13

Each new system family brings changes from its predecessor as technologies shrink, as system structure evolves, and as requirements grow. A remap of an exceptional reliability, availability, serviceability (RAS) design from generation to generation would soon lead RAS characteristics to be inadequate. In this paper, we provide an introduction to some of changes in the IBM z13® and discuss the RAS improvements associated with these changes. We discuss the processor drawer, the memory and cache hierarchy, the I/O firmware stack, the power and thermal systems, the power and service control network, and enhancements to sparing.

Hierarchical random simulation approach for the verification of S/390 CMOS multiprocessors

In this paper an approach is presented for thehierarchical verification of the memory control units, I/O adaptersand processor interconnect units as found in multiprocessorcomputer systems. It is shown how such units could be verifiedbetter and faster by the introduction of random executable timingdiagrams and associated CAD tool support. Furthermore, itis shown how the timing diagrams for the unit network verificationare easily derived from the timing diagrams specified for theunits. The multiprocessor hardware test showed the effectivenessof the proposed verification approach.