K. Paul Muller

POWER7 TM local clocking and clocked storage elements

The design of the clocked storage elements (CSEs) and associated local clocking circuitry is a critical consideration for modern microprocessor projects[1], and the POWER7™ chip[2], designed in a 45nm silicon-on-insulator (SOI) technology, was no exception. The digital logic contained over 2M CSEs, and the design of these elements had a major impact not only on the area, power, and performance of the chip, but also on the reliability, testability, and the ability to debug and optimize the hardware. This paper will focus on the special features added to the CSE design with these considerations in mind.

Understanding Soft Error Resiliency of Blue Gene/Q Compute Chip through Hardware Proton Irradiation and Software Fault Injection

Soft Error Resiliency is a major concern for Petascale high performance computing (HPC) systems. Blue Gene/Q (BG/Q) is the third generation of IBMs massively parallel, energy efficient Blue Gene series of supercomputers. The principal goal of this work is to understand the interaction between Blue-Gene/Qs hardware resiliency features and high-performance applications through proton irradiation of a real chip, and software resiliency inherent in these applications through application-level fault injection (AFI) experiments. From the proton irradiation experiments we derived that the mean time between correctable errors at sea level of the SRAM-based register files and Level-1 caches for a system similar to the scale of Sequoia system. From the AFI experiments, we characterized relative vulnerability among the applications in both general purpose and floating point register files. We categorized and quantified the failure outcomes, and discovered characteristics in the applications that lead to many masking improvement opportunities.

Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation

Fault injection through accelerated irradiation is an effective way to evaluate the overall soft error resiliency of microprocessors. In this work, we report on irradiation experiments on a Blue Gene/Q (BG/Q) compute processor chip running selected applications. Blue Gene/Q is the third generation of IBMs massively parallel, energy efficient Blue Gene series of supercomputers. In the experiments, we found 69 code fails. Out of these, 26 code fails are relevant for the calculation of the mean-time-between-failures (MTBF) for a 20 PetaFLOP, 96 rack system running a comparable workload mix. The expected MTBF for check-stops due to cosmic radiation and alpha particles from chip packaging materials is calculated to be 51 days for sea-level at New York City running the application mix studied. If the most vulnerable application is run exclusively, the projected MTBF is 35 days. These are outstanding results for a machine of this magnitude. The beaming experiment and projected MTBF validate the necessity to include autonomous hardware detection and recovery at the cost of design effort, silicon area and power.

Defect studies on single and bilayer resist systems

Defect detection equipment and procedures to qualify resist systems with regard to defects have been investigated. An analysis was carried out for two bilayer resist systems which were compared to a single layer resist. One of the bilayer resists was developed for the mid‐UV exposure range, the other for deep‐UV. It showed that the pinhole‐limited yield measured by metal–oxide–semiconductor test structures is approximately 10% lower for one of the bilayer resists compared to a single layer resist. The other bilayer resist scheme was compared to a single layer resist with regard to particulates. Here the dry‐developed bilayer resist scheme showed approximately four times higher additive defect densities than the wet‐developed single layer resist. A short dry etch process for opening an anti reflective coating underneath a single layer resist increased the defect densities. Water rinse steps are capable of reducing these defect levels substantially. The dry‐developed resist schemes had higher defect densiti...

Soft error assessments for servers

In order to assess the soft error rate (SER) of a server, it is important to not only quantify the soft error contribution of the individual semiconductor components, but also to account for derating and for SER mitigation like hardening and shielding. Derating describes the fact that not every soft error has an impact. A large number of soft errors vanish based on electrical, logical or timing considerations. They have no impact. Additionally, a server can, to a large degree, be protected from the impact of soft errors by implementing error detection and correction means. In these cases the impact of the soft error is limited to the extra compute time needed for the correction. Summing up the SER contributions from transistors and circuits results in the so-called raw soft error rate, a rate which describes just the bottom layer of the system stack. Powerful protection mechanisms at higher layers can reduce that rate by several orders of magnitude. Awareness of this vertical interaction across the different layers in the system stack leads to servers optimized for robustness.

Soft Error Resiliency Characterization on IBM BlueGene/Q Processor

Soft Error Resiliency (SER) is a major concern for Petascale high performance computing (HPC) systems. In designing Blue Gene/Q (BG/Q) [8], many mechanisms were deployed to target SER including extensive use of Silicon-On-Insulator (SOI), radiation-hardened latches [7,13], detection and correction in on-chip arrays, and very low radiation packaging materials. On the other hand, it is well known that application behavior has major impacts on the masking (or “derating” factor) in system SER calculations. The principal goal of this project is to understand the interaction between BG/Q hardware and high-performance applications when it comes to SER by performing and evaluating a chip irradiation experiment.

Etching on silicon membranes for sub‐0.25‐μm x‐ray mask manufacturing

A multilayer resist (MLR) scheme for the manufacturing of sub‐0.25‐μm x‐ray masks has been developed. MLR facilitates the generation of high‐aspect ratio patterns by electron beam lithography and dry etching. The top three layers are standard MLR structures: a thin imaging resist layer, a thin intermediate layer, and a thick organic underlayer. Previously, others have used spin‐on‐glass or silicon nitride for the intermediate layer [R. Viswanathan, R. Acosta, D. Seeger, H. Voelker, A. D. Wilson, I. Babich, J. Maldonado, J. Warlaumont, O. Vlad’imirsky, F. Hohn, D. Crockatt, and R. Fair, Microelectron. Eng. 9, 93 (1989). A. Huberger, Microelectron. Eng. 5, 3 (1986)]. Sufficiently, thin low‐stress tantalum or tungsten was utilized to provide oxygen reactive‐ion etching resistance. The following layers are utilized under the MLR stack: another thin tantalum or tungsten etch stop layer; a thin gold plating base; and finally a 2.5‐μm silicon membrane. Low image size bias dry etch processes that were successfull...

Long-term data for BTI degradation in 32nm IBM microprocessor using HKMG technology

This paper describes the measured long-term BTI field data from IBM zEnterprise EC12 systems in 32nm High-k/Metal Gate (HKMG) technology using a built-in monitor which is capable of separating the PBTI and the NBTI effects. The BTI monitor is accompanied by a digital thermal sensor in close proximity to correlate the BTI degradation with temperature. Comparable PBTI and NBTI degradation in use condition were observed. Compared with previous z196 microprocessor with 45nm SiON CMOS technology, the new 32nm zEC12 showed more than 2X less BTI degradation. This is attributed to HKMG technology optimization and lower chip voltages.

A case study of electromigration reliability: From design point to system operations

While great efforts have been made to counter the EM reliability degradation due to technology scaling, closer cooperation is needed among semiconductor fabricators, circuit/chip designers and system integrators to ensure final product reliability. This paper presents an example of systematic EM reliability evaluation from design point definition to chip design verification, to system characterization, and finally to EM reliability monitoring from in-field operations.