William V. Huott

On-chip timing uncertainty measurements on IBM microprocessors

Timing uncertainty in microprocessors is comprised of several sources including PLL jitter, clock distribution skew and jitter, across chip device variations, and power supply noise. The on-chip measurement macro called SKITTER (SKew+jITTER) was designed to measure timing uncertainty from all combined sources by measuring the number of logic stages that complete in a cycle. This measure of completed delay stages has proven to be a very sensitive monitor of power supply noise, which has emerged as a dominant component of timing uncertainty. This paper describes the Skitter measurement experiences of several IBM microprocessors including PPC970MP, XBOX360TM, CELL Broadband EngineTM, and POWER6TM microprocessors running different workloads.

6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM

A fully functional read and half select disturb-free 1.2 Mb SRAM is demonstrated. Measured results show an operating range of 0.4 V to 1.5 V and -25degC to 100degC, speed of 6.6+ GHz at IV, 25degC and yield of 90-100%.

Advanced microprocessor test strategy and methodology

This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBMs high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached.

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system

The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm design, while still fitting within the same power envelope. Despite the many difficult engineering hurdles to be overcome, the design team was able to achieve a product frequency of 5.2GHz, providing a significant performance boost for the new system.

Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip

This paper describes the test tool methodology used for the IBM S/390 microprocessor. An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were required. This paper explains the techniques used to accomplish this along with explaining why the method was chosen and how it helped expedite the process.

Circuit design techniques for the high-performance CMOS IBM S/390 parallel enterprise server G4 microprocessor

This paper describes the circuit design techniques used for the IBM S/390® Parallel Enterprise Server G4 microprocessor to achieve operation up to 400 MHz. A judicious choice of process technology and concurrent top-down and bottom-up design approaches reduced risk and shortened the design time. The use of timing-driven synthesis/placement methodologies improved design turnaround time and chip timing. The combined use of static, dynamic, and self-resetting CMOS (SRCMOS) circuits facilitated the balancing of design time and performance return. The use of robust PLL design, floorplanning, and clock distribution minimized clock skew. Innovative latch designs permitted performance optimization without adding risk. Microarchitecture optimization and circuit innovations improved the performance of timing-critical macros. Full custom array design with extensive use of SRCMOS circuit techniques resulted in an on-chip L1 cache having 2.0-ns cycle time.

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chips ground-breaking RAS features are also described, engineered for maximum reliability and system stability.

Testing the 400 MHz IBM generation-4 CMOS chip

This paper describes the design-for-test framework of the 400 MHz CMOS central processor (CP) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe the test sets required to test all portions of the design. This includes built-in self-test, array self-test, weighted random pattern generation, algorithmic pattern generation, and manual patterns. Tests are used to detect faults, static and dynamic, and to debug/diagnose chip failures characteristic to the function under test. The described tests ensure the highest reliability for the components within the system and the same test patterns can be applied from manufacturing all the way to the system level.

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA)

This paper will provide a case study of a particularly difficult debug problem (the Holey Shmoo problem) which developed while designing the IBM System/390 G6 637 MHz microprocessor chip. Resolution of this problem involved the use of some of todays newest DFD/DFT and diagnostics techniques. The discussion of the Holey Shmoo problem and its debug will serve to highlight and demonstrate some of these advanced techniques.

A Low Power and High Performance SOI SRAM Circuit Design with Improved Cell Stability

An embedded CMOS static random access memory (SRAM), including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm partially depleted silicon on insulator (PD SOI) technology. The design features shorter bitlines (16 cells/bitline) along with a thin cell layout and programmable domino read operation. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability. In addition, the SRAM is supplied with multiple supplies: one to the cells, wordline drivers, and level shifters, and the other to the bitline and remaining logic to improve stability and lower power