Werner Kanert

Active cycling reliability of power devices: Expectations and limitations

Abstract Active cycling of power devices, i.e. exposure to repetitive voltage and current pulses, causes power dissipation, resulting in thermo-mechanical loads that can cause different failure mechanisms. This paper focuses on degradation of the metallization. Requirements and customer expectations, using examples from automotive applications, are discussed, contrasting these with the procedures for reliability assessment and their limitations.

Reliability challenges for power devices under active cycling

Power stages are subject to severe stress due to active cycling, resulting in e.g. fast thermal cycling. While some applications require several hundred millions of cycles under normal operation conditions, “disturbances” such as short circuit pose additional challenges. These issues are neither addressed by “classical” silicon wafer technology qualification nor by standard product qualification procedures. Challenges and limitations in applying the principles of Robustness Validation to these issues are discussed.

Degradation of moulding compounds during highly accelerated stress tests. A simple approach to study adhesion by performing button shear tests

High temperature storage can degrade moulding compounds for chip encapsulation to such an extent that the adhesion to surfaces like copper (lead frames) or polyimide (chip coating) decreases drastically causing delamination. Also during normal operation of electronic components heat is generated locally (bond wire or chip surface) degrading the moulding compound and reducing the adhesion which in extreme cases can destroy the metallisation or the bond wires.

Modelling of metal degradation in power devices under active cycling conditions

Metal degradation has recently received increased attention as a failure mechanism in power devices under active cycling conditions, i.e. under repeated pulsed voltage/current loads [1, 2]. Both electro-thermal and thermo-mechanical simulation are indispensable for understanding this mechanisms. The paper presents experimental and simulation data for a dedicated test structure. A suitable lifetime model has to go beyond a simple Coffin-Manson type model to capture the essential influencing parameters.

Investigation of chip-package interaction-looking for more acceleration in product qualification tests

Chip-package interaction is a major concern for product reliability. Temperature cycling is a commonly used stress test to address this issue. The paper shows that temperature shock can substitute temperature cycling for certain failure mechanisms, thereby reducing stress times by a factor of 28 or even more.

Exceptional operative gate voltage induces negative bias temperature instability (NBTI) on n-type trench DMOS transistors

Abstract In some automotive applications, high negative bias is used to faster switch off n-type devices. This exceptional operative gate voltage at relative high temperature can induce instability of device parameters (e.g. threshold voltage, transconductance, saturation current, etc. In this work we will show that positive charge trapping generated under exceptional negative bias can induce large threshold voltage shift. Even if the effect can partially recover during the standard operative condition, nevertheless large Vth, shift are still present and can affect the correct functionality of the device.

Hydrodynamic modeling of avalanche breakdown in a gate overvoltage protection structure

Abstract The breakdown of an overvoltage protection structure is analyzed in the temperature range from 298 to 523 K. The avalanche generation rates are modeled as a function of the carrier and lattice temperature. The generation rates are proportional to the carrier concentration. Careful attention is given to the pre-breakdown regime and to the breakdown process. The importance of various generation processes to the impact process is studied as well as the influence on variations of the ionization threshold energy and of the energy loss during the impact process. It is shown that the carrier generation inside the junction causes adiabatic carrier cooling, which leads to different carrier heating effects at low and high lattice temperature. The behavior of carrier heating at room temperature is strongly affected by the asymmetric field distribution inside the junction. The reason for this is the field dependence of the used trap assisted band to band tunneling model and of the direct band to band tunneling model. It is shown that at room temperature, the onset of hole impact ionization plays an important role for the electron heating. This is different at a temperature of 523 K, where the electrons dominate the onset of impact ionization.

Wire bonding degradation induced by temperature gradients under active cyclic loading

It is well known that high temperature storage can degrade wire bonding contacts significantly due to interdiffusion of pad metal and bonding wire. Looking at harsh applications such as engine management we notice an additional failure mode caused by the temperature gradient during the pulsed active cycling period. Especially when we aim at components with high temperature capability and we substitute the power aluminium metallisation with power copper in order to avoid the formation of lifetime limiting intermetallics, the degradation of wire bonds (Au, Al, Cu) must be assessed with respect to the electrical pulse width, the dissipated power and the number of active cycles, which can exceed 500 millions in automotive applications. This paper presents experimental data with different temperature stress. The time dependent temperature distribution in the device is determined with an electrothermal simulator (TESI). The calculated temperature gradients will be used to enable a thermal-mechanical simulation (ANSYS). As a result a prediction, which kind of pulses can reduce the lifetime of the components under investigation, should be possible.

Analysis of ESD protection structure behaviour after ageing as new approach for system level reliability of automotive power devices

Abstract ESD (electrostatic discharge) protection devices as part of the device pad circuitry of semiconductors are designed for a specific wafer technology and ESD withstanding voltage. After successful qualification they will be released for a usage in high volume products where they must ensure the ESD robustness over the complete product lifetime. All present automotive qualification standards e.g. AEC (automotive electronic council) or JEDEC do not cover the assessment of the typical drifts of the characteristic electrical ESD protection device parameters after application of device specific reliability stress tests under consideration of the target ESD stress [Automotive Electronic Council, AEC-Q100-Rev-F, 2003; Automotive Electronic Council, AEC-Q101-Rev-C, 2005; JEDEC JP-001, Foundry Process Qualification Guideline, 2002]. The paper introduces a methodology to characterize ESD protection diodes after ageing by BTS (bias temperature stress) reliability tests. The used devices are partly ESD pre-stressed before application of the reliability test. The influence of the reliability stress on the ESD robustness is evaluated by using an ESD post-stress. The experimental results are presented and discussed. For ESD protection devices release targets for automotive power applications are defined.

An ignition IGBT with smart functions in chip on chip technology

A smart IGBT for automotive ignition applications is presented. In addition to the well-known advantages of an IGBT, e.g. low saturation voltage, this device uses the capabilities of integration to provide new functions such as current limitation, current flag and voltage feedback. This product is realized by using a chip on chip technology, allowing optimized technologies for the power and logic functions, respectively. Results of first samples are shown.