Ki-Don Lee

Statistics of electromigration early failures in Cu/oxide dual-damascene interconnects

Electromigration (EM) study at temperatures from 325-400/spl deg/C and current densities from 1-2 MA/cm/sup 2/ has determined the failure time characteristics and failure behavior of submicron dual-damascene Cu/oxide interconnects. The test structures used are based on statistical concepts potentially suitable to address the early failure issue in sub-/spl mu/m interconnects and are designed to examine failures occurring only in dual-damascene interconnects. A combination of single and repeated (N=1, 10, 50, and 100) serial chains of nominally identical interconnects are used in conjunction with statistical analysis based on weakest-link concepts (Nelson, 1990) to identify differences in the failure distribution as larger collections of interconnect elements are sampled. In total, nearly 10,000 interconnects were tested using this configuration. Through the use of these multiply-linked interconnect ensembles, statistical evidence of two distinct (weak and strong) failure modes in dual-damascene Cu/oxide interconnects is first reported. The bimodal failures have also been identified with distinct void formation mechanisms that appear characteristic of the dual-damascene interconnect architecture. The weak mode is found to be void formation within the dual-damascene via, while the strong mode is associated with voiding in the dual-damascene trench. The weak mode activation energy is found to be about 1 eV and seems consistent with void formation controlled by interface diffusion between Cu metal and Ta diffusion barrier. These observations using this type of testing methodology confirm the utility of the multi-link approach in electromigration reliability analysis and the detection of early failures.

Electromigration recovery and short lead effect under bipolar- and unipolar-pulse current

Electromigration (EM) of Copper interconnects is studied under unipolar pulse current (UPC) at 1.25 kHz ~ 1.25 MHz and bipolar pulse current (BPC) at 100 kHz ~ 5.0 MHz. For symmetric BPC, where a time-averaged current density (Javg) is 0, we found interconnect failures by EM-induced void formation. This means EM is not fully recovered during the opposite-polarity pulse current. The degree of EM recovery is found to be 0.7 ~ 0.9, where 1 is for full-recovery. Also, the short lead EM effect is investigated under UPC. We found short lead EM lifetimes are modeled by peak current density (Jpeak), instead of Javg. Also, we observed, during the off-time between low frequency pulse currents, mechanical back-stress may reduce the stress gradient built by UPC and increase the EM lifetimes of the short leads.

Electromigration study of Cu/low k dual-damascene interconnects

Electromigration lifetime and failure mechanism have been investigated for Cu/SiLK/spl trade/ interconnects. The activation energies of Cu/SiLK and Cu/oxide were found to be 0.98 eV and 0.81 eV respectively. The activation energy in the range of 0.8 to 1.0 ev suggests a similar mass transport mechanism that can be attributed to interfacial diffusion. The average lifetime of Cu/SiLK was found to be shorter than that of Cu/oxide at test temperatures. The threshold critical length product of Cu/SiLK structures was determined to be about 1/3 of that of Cu/oxide structures. Failure analysis by FIB revealed a distinct failure mode due to lateral Cu extrusion at the low k/oxide etch stop interface. These results together with the increase observed in Joule heating and thermal resistance show that the thermomechanical properties play an important role in controlling the EM reliability of the low k interconnects. Results of this study suggest that the degradation in thermomechanical properties, in particular interfacial adhesion, reduces the back-flow stress, leading to faster mass transport, shorter EM lifetime and Cu extrusion at the anode in the SiLK structures.

A 65 nm CMOS technology for mobile and digital signal processing applications

This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/mm/sup 2/ and a SRAM memory density of 1.4 Mb/mm/sup 2/ using a sub-0.49 /spl mu/m/sup 2/ bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.

Electromigration reliability of Cu interconnects and effects of low K dielectrics

Electromigration (EM) reliability in Cu dual-damascene structures integrated with oxide and low k ILD was investigated using a statistical approach. This approach is efficient in addressing early failures using multi-link structures to sample very large number of interconnect elements. In this paper, we summarize results first on early failures of Cu/oxide structures, then EM characteristics of Cu/low k structures are discussed and compared with Cu/oxide structures. The integration of low k ILD was found to degrade EM performance and to induce a new failure mechanism. These results can be attributed to the thermomechanical properties of the low k ILD and its implication on EM reliability will be discussed.

The impact of partially scaled metal barrier shunting on failure criteria for copper electromigration resistance increase in 65 nm technology

Previous technology nodes employing Cu interconnects have shown an abrupt increase in resistance (R), in excess of the conventional /spl Delta/R/R/sub 0/=20% R increase for the failure criteria (FC). We have observed a different behavior for 65 nm technology electromigration (EM) testing, in which the R increase is sloped after the initial step increase in R. The R step (R-step) increase is less than 20%, so that the sloped region (R-slope) occupies a portion of the 20% FC. We explain the two regions based on the full span void formation (R-step), followed by void growth along the length direction (R-slope). For the first time, we use this sloped region to obtain values for the EM activation energy (Q) and current exponent (n) of dual-damascene Cu interconnects, which agree very well with values obtained from the failure time associated with the initial R step. We propose a new FC corresponding to the time of the initial R-step increase. The increased importance of the R-slope region (RSR) arises from the partially scaled metal barrier thickness, which allows for increased current shunting in the barrier layer. These RSR effects will become even more evident in technology nodes beyond 65 nm.

Via Processing Effects on Electromigration in 65 nm Technology

We investigate the key factors controlling electromigration (EM) in 65 nm technology node. For UP EM (EM for up-directional electron flow at the cathode via), via barrier coverage strongly affects EM reliability for dual-damascene (DD) interconnects. A critical dimension of upper metal patterns caused a shadow effect for the PVD barrier process, which resulted in non-conformal barrier deposition inside the via and a significant degradation in UP EM reliability. The UP EM reliability has been improved with the enhanced barrier coverage inside via and optimized for performance with the reduced overall barrier deposition. For DN EM (EM for down-directional electron flow at the cathode), the via bottom interface turns out to be a key factor controlling EM reliability. The early DN EM failures, in which thin void growth along the via bottom interface fails the interconnect in a short time frame, can be due to poor process controls (i.e., excessive via clean) resulting in a fast diffusion path at the interface. In 65 nm node, UP and DN EM have different via processing effects and need optimization for reliability enhancement

A Variable Current Exponent Model for Electromigration Lifetime Relaxation in Short Cu Interconnects

The short length effect on the electromigration (EM) lifetime is a valuable resource to increase current limits in advanced circuits. We model the effect with variable (current density j sensitive) current exponent n for short leads and calculate how much lifetime margin should be observed for a certain EM rule relaxation. The shorter leads have larger (variable) n so that the EM lifetime decreases faster as the current density increases. We utilize an empirical relationship for the dependence of n on j, which includes a parameter nBS for short leads. We find that to achieve a 2times EM rule relaxation, we must confirm > 25times EM lifetime for nBS = 3 and > 125times for nBS = 5. We illustrate an empirical approach for determining nBS

Observation and restoration of negative electromigration activation energy behavior due to thermo-mechanical effects

An apparent negative activation energy behavior in electromigration lifetime was observed for Cu/low-k single damascene interconnects. We explain this as a result of a fast failure mode by thermo-mechanical damage at low temperatures around 250/spl deg/C. Mechanical strengthening of the via by thickening the sidewall barrier and surrounding it with strong inter-layer dielectric have successfully suppressed the thermo-mechanical failures and restored the activation energy behavior to normal. We show that ensuring thermo-mechanical stability is a key concern for developing reliable high performance interconnects.

Dielectric and Scaling Effects on Electromigration for Cu Interconnects

In summary, multi-link statistical test structures were used to study the dielectric and scaling effects on EM reliability for Cu interconnects. Experiments were performed on dual-damascene Cu interconnects integrated with oxide, CVD low-k, porous MSQ, and organic polymer ILD. The EM activation energy for Cu structures was found to be between 0.8 and 1.0 eV, indicating mass transport is dominated by diffusion at the Cu/SiNx cap-layer interface, independent of ILD. Compared with oxide, the decrease in lifetime and (jL)c observed for low-k structures can be attributed to less dielectric confinement in the low-k structures. An effective modulus B obtained by finite element analysis was used to account for the dielectric confinement effect on EM. The scaling effect was investigated using a statistical approach as a function of line width and barrier thickness for three line widths: 0.25, 0.175, and 0.125 µm corresponding to the 180-, 130-, and 90 nm nodes. Results revealed an intrinsic scaling effect based on the observed line width dependence of the strong-mode EM statistics, which is as expected. However, process-related issues were observed leading to decreasing early failure lifetime and reliability degradation for the 0.125-µm interconnects. The jLc product was found to decrease with decreasing barrier thickness and the trend can be attributed to a decreasing confinement effect, which was estimated using an effective elastic modulus.