Hideki Matsuhashi

Yield Improvement Using a Fast Product Wafer Level Monitoring System

A Scribe Characterization Vehiclereg (CVreg) test chip has been developed to enable a fast turn around mass production yield monitoring system. The test chip design is being placed within the scribe lines of product chip reticles, efficiently utilizing three-dimensional stacking of test structures. During manufacturing, wafer level testing will be executed using pdFasTestreg to ensure test times below 10 minutes per 300 mm wafer. The measurement data will then be analyzed using pdCVtrade to determine yield predictive data like fail rates and defect densities. Also variability data of layer specific parameters like sheet resistance and contact/via resistance will be extracted. Finally, extensive statistical analysis will be run using dataPOWERtrade to derive correlation to product yield as well as lot equipment history

Proactive BEOL yield improvement methodology for a successful mobile product

Mobile products incorporating ever increasing functions and capabilities are often designed on new technologies nodes which can enable smaller chip size and therefore result in profitable production. In order to achieve rapid yield ramp up, new BEOL yield enhancement methodology was implemented for new mobile product introduction which adds preliminary GDS Hot spot analysis to develop test structures, short flow process characterization, and equipment sensor FDC analysis techniques to the traditional methods of yield improvement engineering. The methodology is suited for use in 28nm and beyond technology nodes because the statistically based discovery process can handle changes in process better than the traditional methodologies which rely solely on expert knowledge and limited infrastructure.

Electromigration Study of Cu Dual-damascene Interconnects with a CVD MSQ Low k Dielectric

Electromigration reliability in Cu dual-damascene interconnects with a CVD MSQ low k dielectric was investigated. Statistical studies were carried out using the critical length (LC) test structures containing multi-link line/via elements with varying line lengths. EM lifetime characteristics, critical current density-length product ( j L) c , and failure mechanisms were discussed and compared with Cu/oxide structures. Our results suggested that the diffusion at the cap layer interface was the dominant mechanism for EM mass transport. The confinement effect, in terms of an effective modulus B, can be used to account for the shorter EM lifetime and smaller critical current density-length product ( j L) c observed for Cu/CVD MSQ low k interconnects. Failure analysis by FIB confirmed the presence of multiple failure modes including voiding at the via bottom, Cu extrusion and delamination at Cu/cap layer interface.