Yeong-Taek Lee

55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap structure to suppress junction leakage, which results in 80 ms retention time at 85degC with gate length of 55 nm. Compared to the previous reports, proposed cell transistor shows twice longer retention time even though the gate length shrinks to the half of them. By TCAD analysis, we have confirmed that the improvements are attributed to the superiority of the proposed device structure.

Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

A new NAND string and its read operation scheme using self-boosting as a solution for improving read disturb characteristics of NAND flash memories are proposed. By using the proposed self-boosting read scheme, which includes an optimized bias voltage and adjusted threshold voltage (Vth) of dummy cells, the self-boosted channel voltage prevents soft-programming in unselected memory cells during read operation due to reduced electric field across tunnel oxide. Compared to the conventional scheme this leads to a significant improvement in read disturb characteristics. From simulation and measurement results, the worst electric field of the proposed NAND flash memory during read operation is decreased by around 50% and Vth shifts caused by read disturb is lowered by around 40%, compared to conventional NAND. The proposed NAND was fabricated in a 60 nm NAND technology and successfully demonstrated.

Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation

A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand anisotype junctions in a buried channel structure, we have incorporated charge sharing effect in the quasi-2-D Poisson model. The proposed model correctly predicts the effects of drain bias (V/sub DS/), counter doping layer thickness (x/sub CD/), counter doping concentration (N/sub CD/), substrate doping concentration (N/sub sub/) and source/drain junction depth (x/sub j/), and the new model performs satisfactorily in the sub-0.1 /spl mu/m regime. By using the proposed model on the threshold voltage reduction and subthreshold swing, we have obtained the process windows of the counter doping thickness and the substrate concentration. These process windows are very useful for predicting the scaling limit of the buried channel pMOSFET with known process conditions or systematic design of the buried channel pMOSFET.