Kiichiro Mukai

Hot-electron hardened Si-gate MOSFET utilizing F implantation

A technique is presented for incorporating fluorine (F) into the gate-oxide film, and the subsequent improvement of channel-hot-electron hardness of the resulting MOSFET is reported. This technique uses low-energy F implantation onto the surface of the polysilicon gate-electrode, followed by annealing at 950 degrees C to diffuse F into the gate SiO/sub 2/ toward the SiO/sub 2//Si interface. The improved hot-electron hardness is explained by a model involving a strain relaxation near the SiO/sub 2//Si interface by fluorine incorporation that results from Si-F bond formation.<<ETX>>

Leakage‐Current Increase in Amorphous Ta2 O 5 Films Due to Pinhole Growth during Annealing Below 600°C

Effects of high temperature annealing over the range 400/sup 0/-1000/sup 0/C on the leakage current of tantalum pentoxide (Ta/sub 2/O/sub 5/) films deposited by reactive sputtering are investigated. Leakage current of polycrystalline Ta/sub 2/O/sub 5/ film (annealed above 700/sup 0/C) is about 10/sup 7/-10/sup 8/ times larger than that of as-deposited amorphous film. However, i is found that leakage current in Ta/sub 2/O/sub 5/ film annealed at 600/sup 0/C increases drastically as well, even though the films have no yet recrystallized. TEM observation reveals that pinholes ranging from 5 nm to 15 nm in diameter are formed near the bottom of the depressions in Ta/sub 2/O/sub 5/ film annealed even at 600/sup 0/C. Electrical properties of the Ta/sub 2/O/sub 5/ films are discussed in terms of crystallographic properties such as pinhole growth and grain boundaries.

Dielectric characteristics of fluorinated ultradry SiO2

Improvement of dielectric breakdown characteristics and hot‐electron‐induced interface degradation of metal‐oxide‐semiconductor capacitors having fluorinated ultradry oxides has been demonstrated. The fluorine is introduced through HF surface treatment of Si prior to oxidation. Secondary‐ion mass spectrometry data indicate that SiF distribution is peaked both at the surface of the oxide and at the SiO2/Si interface in the fluorinated ultradry oxide. The possible role of fluorine on the improvement of the dielectric characteristics will be discussed.

Influence of SiO2 at the Ta2O5/Si interface on dielectric characteristics of Ta2O5 capacitors

The influence of SiO2 formed on a Si wafer during Ta2O5 deposition on the dielectric characteristics of Ta2O5 capacitors is investigated. Two types of capacitor were investigated and compared: W/Ta2O5 (27 nm)/W and Al/Ta2O5 (27 nm)/Si capacitors. The thickness of the SiO2 at the interface of Ta2O5/Si is estimated to be 2.4 nm. The W/Ta2O5 (27 nm)/W capacitor is shown to have a dielectric constant of 22 if we assume it is an ‘‘ideal’’ single layer dielectric. On the other hand, for the Al/Ta2O5/Si capacitor if we assume that an SiO2 layer is formed during Ta2O5 deposition we can account for the variation in apparent dielectric constant with thickness and the leakage current as a function of voltage with a model which assumes that when electrons are injected from the SiO2/Si interface, electron charge accumulates at the Ta2O5/SiO2 interface; this reduces the electric field in SiO2 before catastrophic breakdown of the SiO2 film occurs. This results in a relatively small voltage drop (less than 1 V) across th...

Effects of minute impurities (H, OH, F) on SiO/sub 2//Si interface as investigated by nuclear resonant reaction and electron spin resonance

The effects of minute amounts of impurities (H, OH, and F) in SiO/sub 2/ are investigated to obtain a guideline for improving the reliability of MOS devices. To examine the behavior of hydrogen, deuterium (D) is adopted as a tracer. The quantity of deuterium dissolved in SiO/sub 2/ is measured by the D(/sup 3/He,p)/sup 4/He nuclear resonant reaction (NRR) technique. The Influence of the impurities on the SiO/sub 2/-Si interface structure is studied by electron spin resonance (ESR) measurement. Hot-carrier injection with MOS capacitors and transistors are examined to determine the effects of minute impurities on the electrical characteristics of gate SiO/sub 2/ and the correlation of this effect with the NRR and ESR experimental results. It was found that significant amounts of D/sub 2/O are diffused into SiO/sub 2/, even at 200 degrees C, and these dissolved D/sub 2/O molecules are eliminated at temperatures above 700 degrees C. The number of unpaired bonds at the interface increases with decrease of dissolved water in SiO/sub 2/. The disappearance of the interface traps after high-temperature annealing above 800 degrees C is thought to be due to the viscous flow of SiO/sub 2/ and to the interface reoxidation. Reducing the hydrogen and relaxing the interface strain are essential for improving the MOS device endurance against hot carriers. >

Two-step annealing technique for leakage current reduction in chemical-vapor-deposited Ta/sub 2/O/sub 5/ film

A capacitor technology developed to obtain extremely thin Ta/sub 2/O/sub 5/ dielectric film with an effective SiO/sub 2/ film thickness down to 3 nm (equivalent to 11 fF/ mu m/sup 2/) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta/sub 2/O/sub 5/ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O/sub 3/) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O/sub 2/) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps.<<ETX>>

Oxidized Ta/sub 2/O/sub 5//Si/sub 3/N/sub 4/ dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta/sub 2/O/sub 5//Si/sub 3/N/sub 4/ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta/sub 2/O/sub 5//Si/sub 3/N/sub 4/ layers was performed at temperatures higher than 900 degrees C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ mu m/sup 2/, which is equivalent to that of a 6.0- to 6.5-nm-thick SiO/sub 2/. The leakage current at an effective electric field of 5 MV/cm is less than 10/sup -9/ A/cm/sup 2/. Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years. >

The effect of fluorine implantation on the interface radiation hardness of Si‐gate metal‐oxide‐semiconductor transistors

The radiation hardness of fluorinated SiO2/Si interface in metal‐oxide‐semiconductor field‐effect transistors has been found to depend strongly on the amount of fluorine introduced. In this study, the fluorine was introduced by low‐energy F implantation onto the surface of the polycrystalline silicon gate electrode, followed by annealing at 950 °C to diffuse F into the gate SiO2 toward the SiO2/Si interface. The improved radiation hardness is attributed to the strain relaxation near the SiO2/Si interface by fluorine incorporation.

Reliability of Nano-Meter Thick Multi-Layer Dielectric Films on Poly-Crystalline Silicon

A guiding principle of designing double layer dielectric film (SiO2/Si3N4) on poly-Si was established in order to scale down VLSIs. The oxidation of Si3N4 reduces leakage current and defect density. The double layer dielectric film with thinner top oxide layer is harder to breakdown. Hence, the thickness of the top oxide layer must be reduced in order to increase the reliability of double layer dielectrics. The perimeter edge of patterned poly-Si electrode has no affect on the reliability of double-layer dielectric films. As a result. the SiO2/Si3N4 was confirmed to be a high reliable nano-meter thick dielectrics on poly-Si.

Time-dependent dielectric breakdown of ultra-thin silicon oxide

To evaluate the reliability of thin thermally grown oxide films, we examined their intrinsic breakdown characteristics and investigated oxide defects in them using ultra-thin oxides (3-10 nm). It is demonstrated that the breakdown time of oxide films becomes longer as the film thickness is decreased. Through the use of an electron trap generation model, we were able to explain this phenomenon and estimate the breakdown time under low electric field or low current conditions. Furthermore, we were able to determine that, with decreasing film thickness, the defect density of the initial short mode increases, while that of the weak-spot mode decreases.