Noriyuki Sakuma

Abrasive‐Free Polishing for Copper Damascene Interconnection

A complete abrasive‐free process for fabricating copper damascene interconnection has been developed. The process is a combination of newly developed abrasive‐free polishing (AFP) of Cu and dry etching of a barrier metal layer. A new aqueous chemical polishing solution and a polyurethane polishing pad produce complete stop‐on‐barrier characteristics of Cu polishing. The AFP provides a very clean, scratch‐free, anticorrosive polished surface, and the total depth of erosion and dishing is reduced to less than one fifth of that produced by conventional slurries, even after 100% overpolishing. The barrier metal is successfully dry etched by using gas at a high selectivity ratio (more than 10) of barrier metal to . It was found that the developed AFP significantly reduces both Cu line resistance and its deviation. Moreover, AFP can also contribute to cost reduction of chemical mechanical polishing and help solve environmental problems related to waste slurries.

Slurry Chemical Corrosion and Galvanic Corrosion during Copper Chemical Mechanical Polishing

Copper (Cu) corrosion during chemical mechanical polishing (CMP) was controlled in order to improve the Cu damascene interconnect process. Slurry chemical corrosion was found to be enhanced when the slurry was diluted by deionized (DI) water during rinsing just after CMP. Since the corrosion inhibitor, benzotriazole (BTA), reduces the Cu removal rate, adding it to the rinse solution prevents chemical corrosion more effectively than adding it to the slurry. On the other hand, galvanic corrosion occurs at the interface between Cu and the barrier metal, and it can be prevented by selecting appropriate barrier metals. Because the difference between the electrochemical potentials of Cu and the barrier metal is small in the slurry, refractory metals such as Ta, TaN, and TiN were found to be appropriate barrier metals. On the other hand, W, WN, and Ti have large potential differences, so galvanic corrosion was clearly observed when Cu/W damascene interconnects were fabricated.

Effects of Mechanical Parameters on CMP Characteristics Analyzed by Two-Dimensional Frictional-Force Measurement

The effects of mechanical parameters on the characteristics of chemical mechanical polishing ~CMP! were evaluated by directly measuring frictional force acting on a wafer in terms of two components, i.e., the tangential and axial components of the platen’s rotation. It was found that, when the platen and the wafer were rotated at the same speed, the tangential component of the frictional force was dominant. Also, frictional force was in linear proportion with removal rate. Though frictional force increased in linear proportion to down force when mechanical-effect-dominant CMP for silicon ~Si! or silicon dioxide (SiO2) was carried out, it decreased gradually as platen rotational speed was increased. Copper ~Cu! polishing using abrasive-free polishing solutions, a typical example of chemical-effect-dominant CMP, showed much more complex behavior. Namely, dependence of frictional force on down force and on platen rotational speed showed nonlinear characteristics. Even when a nonlinear characteristic slurry was used, it was found that removal rate and frictional force were almost linearly correlated. It can thus be considered that frictional force is a basic parameter to determine CMP characteristics. From these results, an experimental equation was proposed to describe CMP characteristics by modifying Preston’s empirical equation.

Control of Photocorrosion in the Copper Damascene Process

Since chemical mechanical polishing for damascene processes producing copper interconnections is a wet-chemical treatment, corrosion control is indispensable. In addition to ordinary corrosion due to chemical and galvanic reactions with slurries, a new type of corrosion, pattern-specific corrosion, was found. It was clarified to be a kind of anodic corrosion observed only when the damascene process was used to make copper interconnections for active devices, occurring after the metal polishing is completed and the electrodes are electrically separated from each other. A positive potential is generated on the copper electrodes connected to the p + -diffused region against that connected to the n + -diffused region of a p-n junction when the fabrication is carried out in a light environment. The positively biased electrodes corrode quickly, especially in diluted rather than undiluted slurries, resulting in pattern-specific photocorrosion. Less corrosive slurries, especially in diluted state, or corrosion-preventing cleaning methods are therefore needed.

Direct Resist Removal Process from Copper-Exposed Vias for Low-Parasitic-Capacitance Interconnects

A resist stripping process from Cu-exposed vias is developed to reduce the thickness of high permittivity (high-k) SiN in Cu/low-k interconnects. A low power, low temperature O 2 reactive ion etch is proposed to suppress the significant Cu oxidation. Additionally, removing Si contents from the Cu surface is found to be critical, This resist stripping process is successfully applied to the fabrication of Cu/low-k interconnect test devices using silicon oxycarbide (k = 3.3). Low resistance, 0.25 μm diam via connections were achieved. Time dependent dielectric breakdown lifetime tests showed that even 25 nm thick SiN has a sufficient barrier property against Cu diffusion, showing that the SiN thickness reduction is also feasible from the reliability viewpoint. By thinning SiN to less than 25 nm, over 5-10% reduction in k can be achieved even when using the same low-k interlevel dielectric.

Directional Plasma CVD Technology for Sub-quarter-micron Feature Size Multilevel Interconnections

A new plasma chemical vaper deposition (CVD) technology, which provides outstanding film step coverage for sub-quarter-micron, high-aspect-ratio steps on ultralarge semiconductor integrated (ULSI) device surfaces, has been developed. The technology employs a bias plasma CVD deposition system with wide-gap electrodes and reaction gases of triethoxysilane (TRIES) and oxygen. This technology improves the step coverage of SiO2 films by reducing the lateral ledge to less than 60% of that associated with conventional plasma CVD. It also improves the film quality of the SiO2 deposited on the step sidewalls in reducing the sidewall etching rate to less than 50% of that of conventional films. This technology has been applied to an interlevel dielectric (ILD) process in conjunction with organic spin-on-glass (SOG), and the ILD parasitic capacitance was reduced to about 70% of that in conventional plasma CVD. This technology is very promising for application to 0.2 µm feature size ULSI interconnections.

A compact FD-SOI MOSFETs fabrication process featuring Si/sub x/Ge/sub 1-x/ gate and damascene-dummy SAC

A compact FD-SOI CMOS fabrication process and device structure was demonstrated. A new damascene-dummy SAC process enabled to fabricate reliable contacts with ultra-thin SOI layers. We showed that using in-situ-boron-doped Si/sub x/Ge/sub 1-x/ as a gate material, the adequate threshold voltage of FD-SOI was realized.

Mechanical reliability of polyimide insulated interconnections in epoxy encapsulated package under temperature cycle test

Deformation mechanism of polyimide insulated Al alloy lines in epoxy encapsulated package was clarified using temperature cycle test. A shrinkage stress due to the resin on top of the chip creates cracks in the epoxy-resin around the chip corners, and the resin delaminates from the chip to shrink. This causes the polyimide film to tear-off, and the 1st level alloy lines to deform, while upper levels enveloped by the polyimide film move without deformation. Following the model, reliability was improved by preventing the cracks being created in the resin, and/or increasing resin adhesion on chip surface.<<ETX>>