Yuzuru Ohji

Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond

In this paper, a novel shallow trench isolation (STI) process is proposed for 45 nm node technologies and beyond. The major features of this process are the use of a fluorine-doped (F-doped) SiO2 film for gap filling and high-temperature rapid thermal oxidation (HT-RTO) for gate oxidation. Voidless filling of a narrow trench can be realized by F-doped high-density plasma chemical vapor deposition (F-doped HDP-CVD). Moreover, electron mobility degradation caused by STI stress and junction leakage currents can be minimized using F-doped HDP-CVD with HT-RTO. It was also confirmed that compressive stress in the F-doped HDP-CVD sample is smaller in every measurement point around STI than that in the conventional HDP-CVD sample by convergent-beam electron diffraction (CBED). The Si-F bonds in the oxide film play a very important role in stress reduction. By utilizing HT-RTO, Si-F bonds remain and make the SiO2 film in the trench coarse. This technique is a very promising 45 nm node STI scheme with high performance and high reliability.

W-polymetal gate with low W/poly-Si interface resistance for high-speed/high-density embedded memory

A new W-polymetal gate electrode with the structure of W/WN/WSi/poly-Si is proposed. The W-polymetal gate is suitable for high-density memories since it has low resistance and is compatible with the self-aligned contact process. In our study, however, it is found that the interface of W and poly-Si has non-ohmic and quite high resistance in the case wherein only WN is used as a barrier film. This resistance increases the delay in complementary metal-oxide-semiconductor (CMOS) logic circuits and prevents high-speed operation. Our new process includes the deposition of thin WSi on poly-Si, followed by rapid thermal annealing, which results in ohmic and sufficiently low contact resistance between W and poly-Si. It is also demonstrated that selective gate reoxidation is successfully applied for this new structure, and the insertion of thin WSi does not cause any adverse effect on the electrical characteristics of metal-oxide-semiconductor field-effect transistor (MOSFET). This process is promising for high-speed and high-density embedded memory.

Formation of S/D-extension using boron gas cluster ion beam doping for sub-50-nm PMOSFET

Boron doping using gas cluster ion beam (GCIB) is implemented for formation of source/drain-extension (SDE) of pMOSFETs with sub-50-nm gate length. As compared with low energy ion implantation, GCIB is confirmed to produce steep profile of /spl sim/2.5 nm/decade without tail distribution. By simple replacement of low energy boron implantation with GCIB doping, about 20-nm improvement in short-channel effect and almost the same current drivability are obtained for pMOSFETs. Considering that conventional spike RTA and no offset space were used in the fabrication process, GCIB doping is considered to be promising technology for 45-nm node and beyond.

Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond

For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.

Advantages of B/sub 18/H/sub 22/ ion implantation and influence on PMOS reliability

In this paper, the impact of cluster ion (B/sub 18/H/sub x//sup +/) implantation on SDE formation are investigated in detail. It has been shown that B/sub 18/H/sub x//sup +/ ion implantation not only can make ultra-shallow junction for 45 nm node and beyond and but also has self-amorphization property and can reduce the channeling tail in the boron distribution without pre-amorphization implantation. In addition, B/sub 18/H/sub x//sup +/ ion implantation can be expected to reduce a fluctuation of MOSFETs, compared with B/sup +/ implantation. Cluster implantation is the reliability issue by hydrogen atom, because a large amount of hydrogen atoms are simultaneously introduced with boron into the silicon substrate. Moreover, neither the increase of junction leakage current nor influences of hydrogen which is introduced during B/sub 18/H/sub x//sup +/ implantation on PMOS reliability does not occur. The amorphization effect are evaluated by TEM observation and boron and hydrogen profiles by SIMS analysis.

Body bias controlled SOI technology with HTI

As the LSI process technology advances, increase of power consumption for the LSIs becomes major issue because of number of transistors and clock frequencies increase. For a reduction of the power consumption of the LSI, lowering supply voltage technology is one of the effective ways such as applying a dynamic threshold voltage (DT) structure as stated in J. P. Colinge (1987). However, a DT SOI MOSFET with T-shape or H-shape gates has disadvantages of area penalties and a gate parasitic capacitance increase. In this paper we describe actively body-bias controlled (ABC) SOI MOSFET technology with hybrid trench isolation (HTI) based in Y. Hirano et al. (2000). This structure doesnt need the T or H gates and realizes low-voltage and high-speed operation with controlling a body potential.