Seongjae Lee

A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistor

The theoretical and experimental current–voltage characteristics of 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) are discussed. The manufactured 50-nm-gate-length n-type SB-MOSFET shows large on/off current ratio with low leakage current less than 10−4 μA/μm. The saturation current is 120 μA/μm when drain and gate voltage is 1 and 3 V, respectively. The experimental current–voltage characteristics of 50-nm-gate-length n-type SB-MOSFET are fitted using newly developed theoretical model. From the theoretical analysis, the off- and on-current is mainly attributed to the thermionic and tunneling current, respectively. The decrease of tunneling distance at silicon/silicide Schottky junction with the increase of drain voltage gives the increase of tunneling current. This phenomenon is explained by using drain-induced Schottky barrier thickness thinning effect.

Highly-dispersive transparency at optical frequencies in planar metamaterials based on two-bright-mode coupling

Using a planar metamaterial, which consists of two silver strips, we theoretically demonstrate the plasmonic electromagnetically-induced transparency (EIT)-like spectral response at optical frequencies. The two silver strips serve as the bright modes, and are excited strongly by the incident wave. Based on the weak hybridization between the two bright modes, a highly-dispersive plasmonic EIT-like spectral response appears in our scheme. Moreover, the group index is higher than that of another scheme which utilizes the strong coupling between the bright and dark modes.

Electron beam lithography patterning of sub-10nm line using hydrogen silsesquioxane for nanoscale device applications

We investigated novel patterning techniques to produce ultrafine patterns for nanoscale devices. Hydrogen silsesquioxane (HSQ) was employed as a high-resolution negative tone inorganic electron beam resist. The nanoscale patterns with sub-10nm linewidth were successfully formed. A trimming process of HSQ by the reactive ion etcher (RIE) played an important role for the formation of 5nm nanowire patterns. Additionally, hybrid lithography was used to produce various device patterns as well as to minimize proximity effects of electron beam lithography (EBL). Finally, we successfully fabricated triple-gate metal oxide semiconductor field effect transistor (MOSFET) with a gate length of 6nm by using the proposed patterning process.

Characterization of erbium-silicided Schottky diode junction

Trap density, lifetime, and the Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted trap density, lifetime, and Schottky barrier height for hole are determined as 1.5/spl times/10/sup 13/ traps/cm/sup 2/, 3.75 ms and 0.76 eV, respectively. By using the developed method, the interface of the Schottky diode can be evaluated quantitatively.

Characteristics of erbium-silicided n-type Schottky barrier tunnel transistors

The current–voltage characteristics of erbium-silicided n-type Schottky barrier tunnel transistors (SBTTs) are discussed. The n-type SBTTs with 60 nm gate lengths shows typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 105 at low drain voltage regime in drain current to gate voltage characteristics. However, the on/off ratio tends to decrease as the drain voltage increases. From the numerical simulation results, the increase of off-current is mainly attributed to the thermionic current and the increase of drain current is mainly attributed to the tunneling current, respectively. This phenomenon is explained by using drain induced Schottky barrier thickness thinning effect.

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.

Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique

A plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 /spl Omega///spl square/ by the elevated temperature plasma doping of 527 /spl deg/C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.

Simulation of Schottky barrier tunnel transistor using simple boundary condition

The current–voltage characteristics of a Schottky barrier tunnel transistor (SBTT) are simulated by considering the internal voltage drop at the Schottky barrier and using the current continuity condition between the tunneling and channel current. The numerical results show typical behaviors as can be found in many experimental results. From these results, a significantly higher threshold voltage is expected for the SBTT compared to the conventional metal–oxide–semiconductor field-effect transistors, because of the suppression of the tunneling current at low gate voltage. For the nanometer-size device application, a metal gate should be used to decrease the threshold voltage.

Effects of atomistic defects on coherent electron transmission in Si nanowires: Full band calculations

The effects of atomistic imperfections on coherent electron transmission in Si[100] quantum wires a few nanometers wide are investigated using a tight-binding Green function approach. We find a significant suppression in the electron transmission by atomistic imperfections in these extremely narrow wires. Multiple conductance peaks or oscillations can be easily developed by the presence of only several vacancy defects, which can lead to a finite zero-conductance region around the subband edge. Several substitutional defects and surface dangling bonds generally result in decreased, oscillatory conductances with more significant effects found in narrower wires.

Fabrication of fin field-effect transistor silicon nanocrystal floating gate memory using photochemical vapor deposition

The fin field-effect transistor (FET) silicon nanocrystal floating gate memory using the photochemical vapor deposition and the plasma doping processes was proposed. The silicon nanocrystals with a uniform size were formed on a vertical sidewall surface of the fin channel by the photochemical vapor deposition. The plasma doping was applied to form the junctions at the sidewall of the fin source-drain extension regions with a high aspect ratio. The FinFET silicon nanocrystal floating gate memory with a gate length of 100nm was successfully fabricated and it revealed a memory effect as well as a suppressed short-channel effect.