Shinji Aoyama

Extremely low-noise performance of GaAs MESFETs with wide-head T-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-/spl mu/m Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L/sub h/) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anholds method. A current gain cutoff frequency (f/sub T/) and a maximum stable gain (MSG) decrease monotonously as L/sub h/ increases on account of parasitic capacitance. However, the device with L/sub h/ of 1.0 /spl mu/m, which has lower gate resistance than 1.0 /spl Omega/, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMTs.

Three-dimensional passive circuit technology for ultra-compact MMICs

A novel passive circuit technology of a three-dimensional (3D) metal-insulator structure has been developed for ultra-compact MMICs. By combining vertical passive elements, such as a wall-like microwire for shielding or coupling and a pillar-like via connection, with multilayer passive circuits, highly dense and more functional MMICs can be implemented. >

Fabrication of 0.95Sn-0.05Au Solder Micro-Bumps for Flip-Chip Bonding

This letter describes the successful fabrication of a 0.95Sn−0.05Au solder microbump on a compound semiconductor wafer by reflowing of multi-layer metal film. Since the inherent interdiffusion in Au−Sn phases results in the alloying of multi-layer films, the composition of micro-bump is well controlled by the thickness of constituent metal films. The micro-bumps melt at about 220 C, which is close to the lowest eutectic temperature in a Au−Sn system. Solder bonding using 0.95Sn−0.05Au micro-bump is a very useful technique for the flipchip bonding of compound semiconductor devices.

Novel flip-chip bonding technology for W-band interconnections using alternate lead-free solder bumps

A novel lead-free flip-chip technology for mounting high-speed compound semiconductor ICs, which have a relatively severe limitation regarding high-heat treatment, is presented. Solder bump interconnections of 0.95Sn-0.05Au were successfully fabricated by reflowing multilayer metal film at as low a temperature as 220/spl deg/C. The bumps were designed to have a diameter of 36 /spl mu/m with a gap between the chip and the motherboard of 24 /spl mu/m. The electrical characteristics of flip-chip-mounted coplanar waveguide chips were measured. The deterioration in reflection loss in the flip chip mounting was less than 3 dB for frequencies up to W-band.

Controllability of novel Sn/sub 0.95/Au/sub 0.05/ microbumps using interlaminated tin and gold layers for flip-chip interconnection

A flip-chip interconnection technology using novel lead-free solder microbumps with a balling temperature as low as 220 /spl deg/C is presented. Controllability of newly developed Sn/sub 0.95/Au/sub 0.05/ microbumps has been examined experimentally. By varying the bump volume and the diameter of the wettable bump electrodes, Sn/sub 0.95/Au/sub 0.05/ microbumps with heights from 11 /spl mu/m to 37 /spl mu/m were successfully fabricated with a standard deviation of 1.5 /spl mu/m. The deviation of on-chip CPW impedance from 50 /spl Omega/ was lower than 10% for nonmetallization motherboard. The smaller bumps exhibited a better performance since the degradation of reflection properties is ascribed to the bump capacitance, which was estimated 10-20 fF. Because of high process yield and good performance, the flip-chip bonding using Sn/sub 0.95/Au/sub 0.05/ microbumps of the order of 20 /spl mu/m in height may be advantageous for W-band interconnection of InP- or GaAs-based devices.

Three-dimensional interconnect technology for ultra-compact MMICs

Abstract A novel interconnect technology was reviewed, which was developed for three-dimensional (3-D) ultra-compact MMICs. Using O 2 /He RIE for the through hole and trench formation of a thick polyimide insulator layer, low-current electroplating for gold sidewall formation in the through-holes and the trenches, and ion-milling with WSiN metal stopper for gold patterning, a complete three-dimensional metal interconnection structure was built. We call this fabrication method as folded metal interconnection technology with thick insulator(FMIT). The 3-D interconnection structure involves vertical interconnection elements such as a wall-like microwire for shielding or coupling, and a pillar-like via-connection with multi-leveled planar interconnections in a 10-μm-thick polyimide matrix on an IC chip. The structure provides many passive functional elements and circuits in an extremely small area. This technology stages the next-generation of ultra-compact MMICs by offering the circuit designers great design flexibility and higher integration of circuits.

Monolithically integrated photo-receiver with optical waveguides for future 100-Gbit/s class OEICs

Optical waveguides were monolithically integrated with an OEIC to fabricate an ultra-fast optical interconnection and cost-effective photo-receiver module. Additionally, an on-wafer OE-probing system, which can evaluate the optoelectronic performance of the OEIC without dicing, was developed, and we observed a 40-Gbit/s electronic eye diagram from a 40-Gbit/s optical input signal. After dicing the wafer, we packaged the chips using flip-chip bonding by solder micro-bumps. The optical interconnect on a chip self-aligned to a single-mode fiber fixed on the substrate. We achieved an acceptable loss of less than 1 dB with a passive alignment.

Etching method for fabricating ultracompact three-dimensional monolithic microwave integrated circuits

A sophisticated three-dimensional (3D) interconnection structure for ultracompact 3D monolithic microwave integrated circuits (MMICs) has been successfully fabricated by using inductively coupled-plasma etching with a double-layer mask consisting of WSi covered with a Si-containing photoresist. The developed etching method enables us to form via holes to any levels of interconnection simultaneously. The field-effect transistor (FET) parameters change little when the 10-μm-thick polyimide layer is stacked on metal–semiconductor FETs. A unique inductor with a vertical structure is also fabricated by this new etching method. This method will thus result in smaller chip area, higher performance, and greater design flexibility in MMICs.