Suehiro Sugitani

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.

Characteristics including electron velocity overshoot for 0.1- mu m-gate-length GaAs SAINT MESFET's

Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1- mu m-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n/sup +/-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length (a/L/sub g/). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n/sup +/-layers. The average electron velocity for 0.1- to 0.2- mu m-gate-length FETs is estimated to be 3*10/sup 6/ cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f/sub T/ of 93.1 GHz has been attained by the 0.1- mu m SAINT MESFET. >

Three-dimensional MMIC technology for low-cost millimeter-wave MMICs

This paper highlights the key advantages of the three-dimensional (3-D) MMIC technology in the millimeter-wave frequency band and describes recently developed compact 3-D MMICs on GaAs and Si substrates. The 3-D MMIC technology offers high integration levels, compactness, simple design procedures, and short fabrication turn-around time, resulting in millimeter-wave MMICs at greatly reduced cost. This paper also proposes a new methodology for MMIC development based on 3-D/multilayer MMIC technology that accelerates the cost reduction of millimeter-wave MMICs. The new technology achieves compact and highly integrated millimeter-wave MMICs that are extremely cost effective.

A compact V-band 3DMMIC single-chip down-converter using photosensitive BCB dielectric film

A high-density MMIC V-band down-converter that employs the masterslice 3DMMIC technology and photosensitive BCB dielectric film, is presented. The down-converter is structured using an 8/spl times/2 master array in a 1.84 mm/spl times/0.87 mm chip. A down-converter MMIC with H-MESFET with f/sub max/ of 130 GHz demonstrates the gain of 19.3 dB and image rejection ratio of above 18 dB over the frequency range of 56.5 GHz to 59.5 GHz; its associated gain-density is five times higher than that of conventional MMICs.

Extremely low-noise performance of GaAs MESFETs with wide-head T-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-/spl mu/m Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L/sub h/) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anholds method. A current gain cutoff frequency (f/sub T/) and a maximum stable gain (MSG) decrease monotonously as L/sub h/ increases on account of parasitic capacitance. However, the device with L/sub h/ of 1.0 /spl mu/m, which has lower gate resistance than 1.0 /spl Omega/, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMTs.

Three-dimensional passive circuit technology for ultra-compact MMICs

A novel passive circuit technology of a three-dimensional (3D) metal-insulator structure has been developed for ultra-compact MMICs. By combining vertical passive elements, such as a wall-like microwire for shielding or coupling and a pillar-like via connection, with multilayer passive circuits, highly dense and more functional MMICs can be implemented. >

High microwave and ultra-low noise performance of fully ion-implanted GaAs MESFETs with Au/WSiN T-shaped gate

Fully ion-implanted n/sup +/ self-aligned GaAs MESFETs with high microwave and ultra-low-noise performance have been fabricated. T-shaped gate structures composed of Au/WSiN are employed to reduce gate resistance effectively. A very thin and high-quality channel with high carrier concentration can be formed by adopting the optimum annealing temperature for the channel, and the channel surface suffers almost no damage by using ECR plasma RIE for gate formation. GaAs MESFETs with a gate length as short as 0.35 mu m demonstrated a maximum oscillation frequency of 76 GHz. At an operating frequency of 18 GHz, a minimum noise figure of 0.81 dB with an associated gain of 7.7 dB is obtained. A K/sub f/ factor of 1.4 estimated by Fukuis noise figure equation, which is comparable to those of AlGaAs/GaAs HEMTs with the same geometry, reveals that the quality of the channel is very high. >

50-Gbit/s 4-bit multiplexer/demultiplexer chip-set using InP HEMTs

This paper reports on the 50-Gbit/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DMUX) chip-set using InP HEMTs. In order to achieve high and wide-range bit-rate operation, timing design inside the ICs was precisely executed. The packaged MUX and DMUX achieved 50 Gbit/s back-to-back error-free operation for 2/sup 31/-1 pseudo-random bit streams (PRBS). Furthermore, the MUX operated from 4 to 50 Gbit/s with >1 V/sub pp/ output amplitude, and the DMUX exhibited >180-degrees phase margin from 4 to 50 Gbit/s for 2/sup 31/-1 PRBS.

Low-voltage and broadband V-band InP HEMT frequency doubler MMIC

A broadband single-ended V-band InP HEMT frequency doubler MMIC is demonstrated. The fabricated frequency doubler MMIC was operated at 1 V drain supply voltage. The doubler consists of a fundamental input matching circuit and a (proposed herein) fundamental signal rejection filter that also operates as an output matching circuit. The fundamental signal rejection bandwidth of the proposed filtering circuit is more than four times wider than that of a conventional open stub circuit. The doubler MMIC realizes around 0 dB conversion gain and more than 22 dB isolation between the fundamental signal and 2nd harmonic signal over the output frequencies from 54 GHz to 70 GHz. The bandwidth over which both the 3-dB bandwidth and the isolation of 20 dB are satisfied is more than 26 %. The maximum conversion gain is 1.8 dB with 30.4 dB fundamental signal suppression at 60 GHz output frequency. The MMIC occupies just 0.89 mm 2 and consumes only 8 mW.

A compact V-band 3-D MMIC single-chip down-converter using photosensitive BCB dielectric film

A high-density MMIC V-band down-converter that employs the masterslice 3DMMIC technology and photosensitive BCB dielectric film, is presented. The down-converter is structured using an 8/spl times/2 master array in a 1.84 mm/spl times/0.87 mm chip. A down-converter MMIC with H-MESFET with f/sub max/ of 130 GHz demonstrates the gain of 19.3 dB and image rejection ratio of above 18 dB over the frequency range of 56.5 GHz to 59.5 GHz; its associated gain-density is five times higher than that of conventional MMICs.