Yasushi Igarashi

Electromigration properties of copper-zirconium alloy interconnects

Highly reliable interconnects for reducing electromigration failure were demonstrated using a Cu-Zr alloy. The Cu-Zr alloy separates into Cu and precipitates containing Cu-Zr compounds after annealing at 500 °C. The precipitates were observed at grain boundaries and interfaces between the Cu-Zr alloy and surrounding materials. Consequently, because the precipitates prevent the diffusion of Cu, the electromigration lifetimes of the Cu-Zr interconnects are 10 to 100 times longer than those of Cu interconnects. Moreover, the resistivity of the CuZr alloy after precipitation annealing is about 2 μΩ cm because the Zr concentration in the grain interior is below the detection limit of energy-dispersive x-ray spectrometry. Therefore, the Cu-Zr interconnects are suitable for future use in logic devices that will be operated at current densities higher than 1 MA/cm2 and at temperatures higher than 100 °C.

Dry Etching Technique for Subquarter‐Micron Copper Interconnects

A dry etching technique for subquarter-micron Cu interconnects has been developed. A self-aligned passivation film on sidewalls of Cu lines is formed during etching. The thickness of the sidewall film composed of SiON can be controlled precisely by the composition of the etching gas mixture. The addition of NH 3 to the etching gas mixture of SiCl 4 /Cl 2 /N 2 results in a sidewall film free of chlorine. Therefore the sidewall film acts to protect Cu from oxidation and corrosion, and sustains the multilayered structure without film peeling during the fabrication process

A New Mechanism of Failure in Silicon p + /n Junction Induced by Diffusion Barrier Metals

The mechanism of failure of p+/n and n+/p junctions under Al-Si/TiN/Ti and Al-Si/ZrN/Zr systems at contact holes has been investigated. When the total force of the barrier metal in the metallization system, which is defined as the product of the film stress and the film thickness, is larger than 3×105 dyn/cm, the junction leakage current increases on p+/n diodes, but not on n+/p diodes after annealing at 500°C. This increase is caused by the formation of dislocation loops in p+-Si. The formation depends on the annealing temperature, the total force of barrier metal and the B concentration.

Thermal stability of copper interconnects fabricated by dry-etching process

Abstract The thermal stability of Cu interconnects fabricated by dry etching with simultaneous formation of a self-aligned passivation film has been investigated. The passivation film on the sidewall of the interconnects is composed of SiON free from impurities such as Cl. This film acts as a barrier layer to prevent Cu from corroding and oxidizing during any subsequent process, such as formation of a dielectric overcoating. Using this etching process, the Cu interconnect of a TiN/Cu/TiN multilayered structure is formed. The resistivity of the Cu interconnects is about 1.7–2.2 μΩ cm in the width range 0.2–10μm and remains unchanged on annealing up to 700 °C. Diffusion of Cu into the substrate is not observed up to 800 °C annealing. These results demonstrate that the sidewall film prevents diffusion of Cu. Therefore the Cu interconnect covered with TiN and the thick sidewall film is suitable for the ultralarge-scale integration process.

Submicron Ferroelectric Capacitors Fabricated by Chemical Mechanical Polishing Process for High-Density Ferroelectric Memories

Submicron ferroelectric capacitors were fabricated by a damascene process using chemical mechanical polishing (CMP). The fabricated capacitors consisted of SrBi2Ta2O9 (SBT) film with top and bottom electrodes of IrO2 films. The capacitor size was 0.8 µm in diameter, that is, 0.5 µm2 in area. Damage by the fabrication process was not observed in electrical measurements, such as the dependence of remanent polarization on electric field and leakage current properties. The remanent polarization (2Pr) of 5 µC/cm2 at the saturation voltage of 2 V is half that of a large capacitor because the SBT films were composed of single-crystal grains in the bismuth-layered perovskite structure and micro-crystals in many phases including pyrochlore. The crystallinity of the SBT films may be associated with the redistribution of Bi between the SBT thin films and the IrO2 electrodes during the crystallization annealing of SBT.

Thermal Stability of Interconnect of TiN/Cu/TiN Multilayered Structure

The etching process for a Cu interconnect with self-aligned deposition of a thick sidewall film has been developed. This sidewall film acts as a barrier layer to prevent Cu from corrosion and oxidation during the subsequent process, such as formation of a passivation film. Using this etching process, the Cu interconnect of a TiN/Cu/TiN multilayered structure in a submicron feature is formed. Resistivity for the Cu interconnects is about 2 µ Ω cm, and it does not change on annealing up to 700° C. Diffusion of impurities into Cu is not observed up to 800° C annealing. Therefore, the structure of the Cu interconnect, that is, Cu covered with TiN and the thick sidewall film, is suitable for the ULSI process.

High-Reliability Copper Interconnects through Dry Etching Process

A modified high-temperature dry etching technique, which enables anisotropic patterning with a high etching selectivity and self-aligned passivation of a sidewall of an interconnect simultaneously, has been developed for fabrication of sub-quarter-micron Cu interconnects. Resistivities of the resulting Cu interconnects are in the range of 1.7 to 2.2 µΩ cm for the linewidth of 0.2-3.0 µ m. As a result of electromigration (EM) tests, it has been observed that median time to failure (MTF) of the Cu interconnects depends on their linewidth. This behavior is considered to be caused by their grain structure, such as a bamboo-type structure for linewidths narrower than 0.3 µ m. In comparison with a MTF of a conventional Al-1%Si line, these Cu interconnects have at least 100 times longer lifetime. Activation energy for EM damage of the 0.7-µ m-wide line is 0.88 eV.

Suppression of migration in Al conductors by lowering deposition temperature in plasma CVD SiN passivation

Storage tests at elevated temperatures and electromigration tests were performed on aluminum (Al) conductors covered with silicon nitride passivation deposited at low temperature by plasma enhanced chemical vapor deposition (CVD). It was shown that the migration such as stress induced voiding and electromigration can be reduced by lowering the deposition temperature of the passivation layer. The discontinuity failure by voiding is reduced and leads to increased lifetimes. The generation of notchlike voiding is also reduced. Improvements were attributed to the reduction of thermally induced stress in Al conductors at test temperatures. The plasma silicon nitride passivation deposited at low temperature was preferable as a candidate for passivation layers in devices with submicron Al conductors.<<ETX>>

Effects of bottom electrode conditions on ferroelectric properties of SrBi2Ta2O9 thin films

The effect of adhesion layers under the bottom electrodes on ferroelectric characteristics of SrBi2Ta2O9 (SBT) thin films synthesized by sol-gel method was investigated. The remanent polarization (2Pr) of SBT films was found to be smaller for the tantalum oxide (TaOx) adhesion layer than for the titanium oxide (TiOx) adhesion layer, whereas the coercive voltage (2Vc) was larger for the TaOx adhesion layer than for the TiOx adhesion layer. The difference was due to a larger c-axis distribution of crystals in the SBT film on Pt with the TaOx layer than with the TiOx layer. Moreover, the imprint characteristics of SBT capacitors on the TaOx layer were better than those on the TiOx layer because the 2Vc in SBT capacitors was larger for the TaOx layer than for the TiOx layer, and the polarization stability against the hysteresis shift was better for the TaOx layer than for the TiOx layer.

Influence of annealing ambients on ZrSi2 formation

Abstract The formation of zirconium silicide was studied in many kinds of annealing ambients, i.e., Ar-H 2 , Ar-O 2 , N 2 -O 2 , Ar-N 2 -O 2 , and Ar-air. When the ambient involves both N 2 and O 2 , such as Ar-N 2 -O 2 and N 2 -O 2 , in the range of [N 2 ]/([N 2 ] +[O 2 ])>0.9, the film resistivity becomes higher than that of the Ar-O 2 case, even at the same O 2 concentration. This is because a thick ZrO x N y layer is formed on the ZrSi 2 layer. When the ratio of [N 2 ]/([N 2 ] + [O 2 ]) in the Ar-N 2 -O 2 ambient is less than 0.9, the films are partially peeled off from the substrate. The resistivity of a film annealed in the Ar-air ambient is very high at even a few ppm O 2 . This is because the film peels off and then the oxidation of the peeled film is accelerated by a small amount of H 2 O in air.