Kiwook Lee

Application of through mold via (TMV) as PoP base package

In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP base package may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts, reduced thickness, tight warpage control and higher levels of integration within the PoP base package. This paper introduces a new PoP base package structure that addresses the challenges of next generation applications. A PoP base package with through mold vias (TMV) will be described. Package flatness and package stacking results will be presented and advantages of TMV technology will be reviewed.

Intermetallic compound and Kirkendall void growth in Cu pillar bump during annealing and current stressing

Cu pillar bump with eutectic SnPb was annealed and the micro structures were observed by scanning electron microscopy. Both of Cu₆Sn₅ and Cu₃Sn grew following parabolic rate law at 120 and 150degC. At 165degC, Cu₆Sn₅ growth was stagnated while Cu₃Sn growth rate was increased after 160 hour when all Sn was consumed. Kirkendall void was formed because of different diffusivities of Cu and Sn. The activation energies of Cu₆Sn₅, Cu₃Sn, and Kirkendall void growth were 1.77, 0.72, and 0.36 eV respectively. Intermetallic compound (IMC) growths during 150degC annealing and in current stressing condition were observed to investigate the effect of current stressing. In current stressing condition, the temperature was 150degC and the current density was 5 times10⁴ A/cm². IMC growth in current stressing condition was faster than that during annealing because of electron wind force.

TSV integration on 20nm logic Si: 3D assembly and reliability results

Each new technology node brings new design and technology challenges making it harder to maintain Moores law in a cost effective way. Maintaining cost effectiveness is becoming a major challenge for IDMs, fabless companies and foundries. 3D/2.5D technologies offer some unique advantages over traditional scaling such as higher power efficiency, higher bandwidth and heterogeneous integration which can arguably lower design complexity and manufacturing cost. While advantages of 3D ICs are well known, adoption of this technology has been shifting out due to several technological challenges and manufacturing supply chain concerns. In this paper, 3D packages are realized by stacking mechanical Wide IO memory onto a 20nm low power mobile logic die with through silicon vias (TSVs). This architecture is very promising for mobile application as it can provide lower power consumption, higher bandwidth and faster communication between memory and logic with a smaller form factor. Various technical challenges that were addressed while building a 3D package along with its process and reliability results, both wafer level and package level, are discussed in this paper.

Interfacial microstructure and mechanical reliability of Cu pillar/Sn-3.5Ag bump for 3D packages

Interfacial microstructure and mechanical reliability of Cu pillar/Sn-3.5Ag microbumps during annealing conditions were systematically and quantitatively evaluated. The IMC growth followed a linear relationship with the square root of the annealing time, which means that the IMC growth was controlled by a diffusion mechanism. The shear strength and IMC thickness increased quadratically with annealing time at 150°C, while the amount of solder decreased. It was clearly revealed that there exist strong correlations among IMC growth kinetics, shear strength, and fracture modes in Cu/solder microbumps.

Current stressing effects on the reliability of Cu pillar bump with shallow solder

The intermetallic compound (IMC) growths of Cu pillar bump with shallow solder (thin Sn thickness) were investigated during annealing or current stressing condition. After reflow, only Cu6Sn5 was observed, but Cu3Sn formed and grew at Cu pillar/Cu6Sn5 interface with increasing annealing and current stressing time. The kinetics of IMC growth changed when all Sn in Cu pillar bump was exhausted. The complete consumption time of Sn phase in electromigration condition was faster than that in annealing condition. Under current stressing condition, intermetallic compound growth was significantly enhanced mainly due to the joule heating effects. Kirkendall void was observed at the interface of Cu pillar/Cu3Sn and it affected the mechanical reliability of Cu pillar bumps, which was estimated by die shear test.

Reliability of Cu pillar bump for flip chip and 3-D SiP

Cu pillar bumps with eutectic SnPb solder were annealed and their microstructures were investigated. Linear relationship was observed between thickness of intermetallic compounds (IMCs: Cu6Sn5, Cu3Sn) and square root of time at 120 and 150degC. Kirkendall voids, formed by the diffusivity differences between Cu and Sn, were observed near the interface between Cu and Cu3Sn. There was a change in slope of the linear relationship between IMCs thickness and square root of time at 165degC when all Sn was consumed. Cu6Sn5 growth rate was retarded, while Cu3Sn growth rate was accelerated. The activation energies for Cu6Sn5, Cu3Sn, and Kirkendall voids growth were estimated to be 1.77, 0.72, and 0.36 eV, respectively. The microstructures of Cu pillar bumps with pure Sn were investigated by in-situ scanning electron microscopy under annealing and high current-stressing conditions. It was found that IMC growth rate under annealing condition obeyed parabolic rate law, while that under high current-stressing condition IMC growth rate did not obeyed linear rate law. IMC growth rate under high-current stressing condition was faster than that under annealing condition which is presumed to be caused by the atomic migration enhancement due to the electron wind force.

Effect of Thermal Aging on Intermetallic Compound Growth Kinetics of Au Stud Bump

Microstructural evolution and the intermetallic compound (IMC) growth kinetics in an Au stud bump were studied via isothermal aging at 120, 150, and 180 C for 300hrs. The AlAu phase was observed in an Al pad/Au stud interface, and its thickness was kept constant during the aging treatment. AuSn, AuSn , and AuSn phases formed at interface between the Au stud and Sn. AuSn , AuSn /AuSn , and AuSn phases dominantly grew as the aging time increased at 120 C, 150 C, and 180 C, respectively, while (Au,Cu) Sn / Cu Sn phases formed at Sn/Cu interface with a negligible growth rate. Kirkendall voids formed at AlAu /Au, Au/Au-Sn IMC, and Cu Sn/Cu interfaces and propagated continuously as the time increased. The apparent activation energy for the overall growth of the Au-Sn IMC was estimated to be 1.04 eV.

A Study on the Fabrication of STS 316L Films by Ion Beam Deposition with Ion Source

The thin films of 316L stainless steel were made on glass and S45C substrate by Ion beam assisted deposition with reactive atmosphere of argon and nitrogen. The films were deposited at the various conditions of ion beam power and the ratios of Ar/gas. Properties of these films were analyzed by glancing x-ray diffraction method(GXRD), AES, potentiodynamic test, and salt spray test. The results of GXRD showed that austenite phase could be appeared by ion beam treatment and the amount of austenite phase increased with the amount of nitrogen gas. The films without plasma ion source treatment had the weak diffraction peak of ferrite phase. But under the Ar plasma ion beam treatment, the strong diffraction peaks of ferrite phase were appeared and the grain size was increased from 12 to 16 nm. Potentiodynamic polarization test and salt spray test indicated that the corrosion properties of the STS 316L films with nitrogen ion source treatment were better than bulk STS 316L steel and STS 316L films with Ar ion source treatment.