Jaedong Kim

Application of through mold via (TMV) as PoP base package

In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP base package may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts, reduced thickness, tight warpage control and higher levels of integration within the PoP base package. This paper introduces a new PoP base package structure that addresses the challenges of next generation applications. A PoP base package with through mold vias (TMV) will be described. Package flatness and package stacking results will be presented and advantages of TMV technology will be reviewed.

Study of interconnection process for fine pitch flip chip

Today, flip chip technology is a main stream of interconnection in microelectronic packaging and market forces continue to drive toward finer pitch interconnections. In this paper, fine pitch flip chip (FPFC) interconnection technology (i.e., less than 60um pitch) will be described. Two types of 50um pitch bump (Au stud & Cu pillar) will be evaluated and two different flip-chip (FC) bonding methods will be studied. Package structures of bare die flip-chip CSP (chip scale package) and also over molded version will be studied for reliability performance and volume assembly fit. For characterization, structure analysis will be performed at each reliability read point. Finally this paper will conclude by identifying the most robust bonding method for the FPFC devices.

Intermetallic compound and Kirkendall void growth in Cu pillar bump during annealing and current stressing

Cu pillar bump with eutectic SnPb was annealed and the micro structures were observed by scanning electron microscopy. Both of Cu₆Sn₅ and Cu₃Sn grew following parabolic rate law at 120 and 150degC. At 165degC, Cu₆Sn₅ growth was stagnated while Cu₃Sn growth rate was increased after 160 hour when all Sn was consumed. Kirkendall void was formed because of different diffusivities of Cu and Sn. The activation energies of Cu₆Sn₅, Cu₃Sn, and Kirkendall void growth were 1.77, 0.72, and 0.36 eV respectively. Intermetallic compound (IMC) growths during 150degC annealing and in current stressing condition were observed to investigate the effect of current stressing. In current stressing condition, the temperature was 150degC and the current density was 5 times10⁴ A/cm². IMC growth in current stressing condition was faster than that during annealing because of electron wind force.

Board level reliability assessments of thru-mold via package on package (TMV™ PoP)

In recent years, Package-on-package (PoP) has been adopted as major application package platform in 3D integration of logic and memory devices. However, as electronic technology developed, higher technology requirements are requested in packaging. Amkor Technology, Inc introduced the next generation PoP solution to meet the next generation technology requirements in 2008 by the using of TMV™ technology which incorporates a laser ablation process that is conducive to current matrix-molded semiconductor assembly techniques. The next generation PoP platform named as TMV™ PoP has been qualified in all package level qualification tests. Also in board level reliability tests, BLR TC & drop performances are similar or better than those of the conventional PoP.

A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

A chip-package hybrid DLL and clock distribution network provides low-jitter clock signals by utilizing separate supply connections and lossless package layer interconnections instead of on-chip global wires. The hybrid scheme has 78ps/sub co/ jitter and under 240mV digital noise at 500MHz, while a conventional scheme has a 172ps/sub p-p/ jitter under the same conditions.

MEMS packaging technology using a cavity structure for mass production

Lower cost package for microelectromechanical systems (MEMS) have been required, because the cost portion of the MEMS package is more than 30% of the cost of a MEMS product. For the reason, cost effective MEMS packaging platforms are proposed in this paper for high volume production. Two package platforms are developed using an epoxy molding compound (EMC) onto copper (Cu) pre-plated lead frames (L/F). One is a cavity wall type with attaching a flat lid. The other is an in-frame type with attaching a folded cap lid. Finite element method (FEM) numerical modeling is performed to anticipate the mechanical warpage and stress of the packages. The finally assembled packages are tested for wire pulling, lid pulling, hermetic test, and reliability tests. The wire bonding strength was improved in about 40% using plasma cleaning before wire bonding. Through a lid pulling test, the lid bonding strength of 2.40 kgf in average was obtained using an epoxy adhesive. Finally, all samples of the packages passed the reliability tests of the TC, HAST and HST, standardized by JEDEC (joint electron device engineering council). Also, this cavity package showed excellent hermeticity through leak test.

Interfacial microstructure and mechanical reliability of Cu pillar/Sn-3.5Ag bump for 3D packages

Interfacial microstructure and mechanical reliability of Cu pillar/Sn-3.5Ag microbumps during annealing conditions were systematically and quantitatively evaluated. The IMC growth followed a linear relationship with the square root of the annealing time, which means that the IMC growth was controlled by a diffusion mechanism. The shear strength and IMC thickness increased quadratically with annealing time at 150°C, while the amount of solder decreased. It was clearly revealed that there exist strong correlations among IMC growth kinetics, shear strength, and fracture modes in Cu/solder microbumps.

Current stressing effects on the reliability of Cu pillar bump with shallow solder

The intermetallic compound (IMC) growths of Cu pillar bump with shallow solder (thin Sn thickness) were investigated during annealing or current stressing condition. After reflow, only Cu6Sn5 was observed, but Cu3Sn formed and grew at Cu pillar/Cu6Sn5 interface with increasing annealing and current stressing time. The kinetics of IMC growth changed when all Sn in Cu pillar bump was exhausted. The complete consumption time of Sn phase in electromigration condition was faster than that in annealing condition. Under current stressing condition, intermetallic compound growth was significantly enhanced mainly due to the joule heating effects. Kirkendall void was observed at the interface of Cu pillar/Cu3Sn and it affected the mechanical reliability of Cu pillar bumps, which was estimated by die shear test.

Reliability of Cu pillar bump for flip chip and 3-D SiP

Cu pillar bumps with eutectic SnPb solder were annealed and their microstructures were investigated. Linear relationship was observed between thickness of intermetallic compounds (IMCs: Cu6Sn5, Cu3Sn) and square root of time at 120 and 150degC. Kirkendall voids, formed by the diffusivity differences between Cu and Sn, were observed near the interface between Cu and Cu3Sn. There was a change in slope of the linear relationship between IMCs thickness and square root of time at 165degC when all Sn was consumed. Cu6Sn5 growth rate was retarded, while Cu3Sn growth rate was accelerated. The activation energies for Cu6Sn5, Cu3Sn, and Kirkendall voids growth were estimated to be 1.77, 0.72, and 0.36 eV, respectively. The microstructures of Cu pillar bumps with pure Sn were investigated by in-situ scanning electron microscopy under annealing and high current-stressing conditions. It was found that IMC growth rate under annealing condition obeyed parabolic rate law, while that under high current-stressing condition IMC growth rate did not obeyed linear rate law. IMC growth rate under high-current stressing condition was faster than that under annealing condition which is presumed to be caused by the atomic migration enhancement due to the electron wind force.