Kiyofumi Ochii

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell

A 4-Mb (512 K words by 8-b) CMOS static RAM (SRAM) with a PMOS thin-film transistor (TFT) has been developed. The RAM can obtain a much larger data-retention margin than a conventional high-resistive load-type well by using the PMOS TFT as a memory cell load. An internal voltage down-converter architecture with an external supply voltage-level sensor not only realizes a highly reliable 0.5- mu m MOS transistor operation but also a sufficiently low standby-power dissipation characteristic for data battery-backup application. A self-aligned equalized level sensing scheme can minimize the sensing delay for a local sense amplifier to drive a large load capacitance of a global sensing bus line. The RAM is fabricated using a 0.5 mu m, triple-poly, and double-aluminum with dual gate-oxide-thickness CMOS process technology. The RAM operates under a single 5-V supply voltage with 23-ns typical address access time and 20- and 70-mA operation current at 10 and 40 MHz, respectively. >

An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell

A fully static 8K word by 8 bit CMOS RAM, with a six-transistor CMOS cell structure to achieve an extremely low standby power of less than 50 nW has been developed. A 2 /spl mu/m, double polysilicon CMOS process was utilized to realize a 19/spl times/22 /spl mu/m cell size. Redundance technology with polysilicon laser fuses was also developed for improving fabrication yield with relatively large chip size, i.e. 5.92/spl times/7.49 mm. In addition, for reducing operational power dissipation while maintaining fully static operation from outside on the chip, an internally clocked low-power circuit technology using row address transition detectors was employed, which results in only 15 mW operational power at 1 MHz by cutting off all DC current paths. The RAM offers an 80 ns address access time.

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz. >

A 15nW standby power 64Kb CMOS RAM

A FULLY STATIC 8K x 8b CMOS RAM, with a six-transistor structure, an internally-clocked low-power circuit and a redundancy technique, together with double polysilicon CMOS processing will be covered. The RAM offers typically 15mW power dissipation at lMHz operation, 50nW for standby and 8011s typical access time. Recently, it has been realized that a resistive load NMOS cell with CMOS peripheral circuits can offer high density, high speed and low active power for static RAMs. However, even with an extremely high resistive load, standby power level is limited to around 25pW typically, for 16Kb integration?, while sacrificing process margin. On the other hand, a six-transistor CMOS memory cell can provide standby current three orders of magnitude smaller, while maintaining much wider temperature and voltage range as well as noise margin. Obviously, a penalty for the performance is larger cell area.

A 9 ns 4 Mb BiCMOS SRAM with 3.3 V operation

A description is given of a 4-Mb TTL (transistor-transistor logic) SRAM in 0.5- mu m BiCMOS technology which uses scaled-down features of optimized MOS and bipolar transistors and BinMOS circuits to achieve 9 ns access and low-power 3.3-V operation of a 16-b organization. The SRAM block diagram is presented, and the 0.5- mu m triple-polysilicon and double-metal BiCMOS process is summarized.<<ETX>>

An 8 ns 1 Mb ECL BiCMOS SRAM

A description is given of a 1-Mb*1ECL (emitter-coupled-logic) SRAM (static random access memory) fabricated with a 0.8- mu m BiCMOS technology which has 8-ns access time and is 10K-I/O (input/output) compatible. To achieve sub-10 ns address access time and low power consumption, an ECL CMOS level converter, a bit-line peripheral circuit, and an automatic power saving function are employed. Details of the 0.8- mu m BiCMOS process technology are summarized, and an oscilloscope photograph shows 8-ns address access time under nominal conditions. The RAM characteristics are summarized.<<ETX>>

A 17ns 64K CMOS RAM with a schmitt trigger sense amplifier

This paper will describe a CMOS SRAM using a four-transistor cross-coupled flip-flop memory cell with a high resistivity load composed of the second poly-Si. Cell is 12.5μm× 21.5μm. Die is 3.86mm×6.99mm that can De packaged in a 300 mil wide 22 pin plastic DIP.

Fully static 16Kb bulk CMOS RAM

A coplanar Si-gate CMOS process used in the design of a fully static 16Kb bulk CMOS RAM with a six-transistor cell will be covered. RAM offers a typical 95ns access time with 200mW power dissipation and 1μW standby power.

SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober

The reliability and performance of SRAM are highly dependent on the cell stability, and the stability is affected by parasitic resistances in a memory array. The parasitic resistances result in a correlative behavior of the cells and are difficult to analyze and measure in a memory array. This topic has been rarely discussed in the literature. In this paper, the correlative behavior is analyzed by trajectories in a phase diagram composed by cell storage nodes. Electrical probing is done by the data holding test. The validity of the analysis and the probing method is confirmed by the measurements on a 0.8-/spl mu/m 1-Mb CMOS SRAM. An aspect of the cell scaling with attention to the parasitic resistance is also discussed.

TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs

Thin-film transistor (TFT) cell technology has been proposed for high-density SRAM cells. It was demonstrated that when utilizing this technology both low standby current and high cell stability are obtained simultaneously without increasing cell size. TFT characteristics required for 4-Mb SRAMs are discussed, and it is noted that improvements in packing density while maintaining low standby current cause difficulties in achieving stable cell characteristics in very-high-density SRAMs using a conventional high-resistance load cell (Hi-R cell). In SRAMs with feature size of 0.5 &mu;m or less, operation voltage is lowered due to severe hot-carrier-induced degradation in MOSFETs. To achieve desirable characteristics for future SRAMs, the grain size dependence of TFT characteristics was investigated. It is shown that low-temperature regrowth of &alpha;-Si is a promising method to obtain very large grain size, resulting in excellent TFT characteristics. TFT technology was applied to a 4-Mb SRAM with a new cell structure, where the drain regions of driver transistors form gate electrodes for TFTs. The 4-Mb SRAM was successfully fabricated, verifying the feasibility and validity of the TFT technology