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Featured researches published by Kiyofumi Sakurai.


international solid state circuits conference | 2007

A 56-nm CMOS 99-

Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Yoshihisa Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; Masayuki Ichige; Kazuo Hatakeyama; Shinichi Tanaka; Teruhiko Kamei; Jia-Yi Fu; Adi Cernea; Yan Li; Masaaki Higashitani; Gertjan Hemink; Shinji Sato; Ken Oowada; Shih-Chung Lee; Naoki Hayashida; Jun Wan; Jeffrey W. Lutze; Shouchang Tsao; Mehrdad Mofidi; Kiyofumi Sakurai

A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed. This is the worlds first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum2 per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size


IEEE Journal of Solid-state Circuits | 1993

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Natsuki Kushiyama; Shigeo Ohshima; D. Stark; H. Noji; Kiyofumi Sakurai; Satoru Takase; Tohru Furuyama; R.M. Barth; A. Chan; J. Dillon; James A. Gasbarro; M.M. Griffin; Mark Horowitz; T.H. Lee; Victor E. Lee

A 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was achieved by designing a DRAM core with a very high internal column bandwidth, and coupling this core with a block-oriented, small-swing, synchronous interface that uses skew-canceling clocks. The DRAM has a 1-kbyte*2-line sense-amp cache and is assembled in a 32-pin vertical surface-mount-type plastic package. The measurement results clearly verified the 500-Mbyte/s data rate. >


IEEE Journal of Solid-state Circuits | 2006

8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

Takahiko Hara; Koichi Fukuda; Kazuhisa Kanazawa; Noboru Shibata; Koji Hosono; Hiroshi Maejima; Michio Nakagawa; Takumi Abe; Masatsugu Kojima; Masaki Fujiu; Yoshiaki Takeuchi; Kazumi Amemiya; Midori Morooka; Teruhiko Kamei; Hiroaki Nasu; Chi-Ming Wang; Kiyofumi Sakurai; Naoya Tokiwa; Hiroko Waki; Tohru Maruyama; Susumu Yoshikawa; Masaaki Higashitani; Tuan Pham; Yupin Fong; Toshiharu Watanabe

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.


international solid-state circuits conference | 2006

A 500-megabyte/s data-rate 4.5 M DRAM

Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Y. Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; Masayuki Ichige; Kazuo Hatakeyama; Sumio Tanaka; Teruhiko Kamei; Jia-Yi Fu; Adi Cernea; Yan Li; Masaaki Higashitani; Gertjan Hemink; Shinji Sato; Ken Oowada; Shih-Chung Lee; N. Hayashida; Jun Wan; Jeffrey W. Lutze; Shouchang Tsao; Mehrdad Mofidi; Kiyofumi Sakurai

Fabricated in 56nm CMOS technology, an 8Gb multi-level NAND Flash memory occupies 98.8mm2, with a memory cell size of 0.0075mum/b. The 10MB/s programming and 93ms block copy are also realized by introducing 8kB page, noise-cancellation circuits, external page copy and the dual VDD scheme enabling efficient use of 1MB blocks


symposium on vlsi circuits | 1992

A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

Natsuki Kushiyama; Shigeo Ohshima; D. Stark; Kiyofumi Sakurai; Satoru Takase; T. Furuyuma; B. Barth; J. Dillon; James A. Gasbarro; M. Griffin; Mark Horowitz; V. Lee; W. Lee; W. Leung

A novel 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate has been designed. This high data-rate has been achieved by coupling a very high internal column bandwidth DRAM core with a very high internal column bandwidth, and coupling this core with a block oriented, small-swing, synchronous interface that uses skew canceling clocks. The DRAM has a 1-kbyte*2 line sense amplifier cache. This DRAM is assembled in a 32-pin vertical surface mount type plastic package.<<ETX>>


international solid-state circuits conference | 2009

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput

Takuya Futatsuyama; Norihiro Fujita; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Teruhiko Kamei; Hiroaki Nasu; Makoto Iwai; Koji Kato; Yasuyuki Fukuda; Naoaki Kanagawa; Naofumi Abiko; Masahide Matsumoto; Toshihiko Himeno; Toshifumi Hashimoto; Yi-Ching Liu; Hardwell Chibvongodze; Takamitsu Hori; Manabu Sakai; Hong Ding; Yoshiharu Takeuchi; Hitoshi Shiga; Norifumi Kajimura; Yasuyuki Kajitani; Kiyofumi Sakurai; Kosuke Yanagidaira; Toshihiro Suzuki; Yuko Namiki; Tomofumi Fujimura; Man Mui

NAND flash memories are used in digital still cameras, cellular phones, MP3 players and various memory cards. As seen in the growing needs for applications such as solid-state drives and video camcoders, the market demands for larger-capacity storage has continuously increased and NAND Flash memories are enabling a wide range of new applications. In such situations, to achieve larger capacity at low cost per bit, technical improvement in feature-size scaling [1], multi-bit per cell [2,3] and area reduction are essential.


IEEE Journal of Solid-state Circuits | 1989

500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

Yohji Watanabe; Takashi Ohsawa; Kiyofumi Sakurai; Tohru Furuyama

The capacitance-resistance (CR) delay circuit technology assures full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions and thus realizes a fast access time. A noise compensation scheme is used to generate a constant delay even under the power supply line noise. The circuit was applied to a 4 Mbit dynamic RAM (DRAM) peripheral circuit. As a result, timing loss as well as malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time, compared with a conventional design using normal inverter chains, have been achieved. >


international solid-state circuits conference | 2011

A 113mm2 32Gb 3b/cell NAND flash memory

Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Takeshi Ogawa; Makoto Iwai; Osamu Nagao; Junji Musha; Takatoshi Minamoto; Kosuke Yanagidaira; Yuya Suzuki; Dai Nakamura; Yoshikazu Hosomura; Yuka Furuta; Mai Muramoto; Rieko Tanaka; Go Shikata; Ayako Yuminaka; Kiyofumi Sakurai; Manabu Sakai; Hong Ding; Mitsuyuki Watanabe; Yosuke Kato

NAND flash memories are now indispensable for our modern lives. The application range of the storage memory devices began with digital still cameras and has been extended to USB memories, memory cards, MP3 players, cell phones including smart phones, netbooks, and so on. This is because higher storage capacity and lower cost are realized through means of technology scaling every year. Emerging markets, such as solid-state drives (SSDs) and data-storage servers, require lower bit cost, higher program and read throughputs, and lower power consumption


IEEE Journal of Solid-state Circuits | 1990

A new CR-delay circuit technology for high-density and high-speed DRAMs

J.-I. Okamura; Y. Okada; Masaru Koyanagi; Yoshiaki Takeuchi; M. Yamada; Kiyofumi Sakurai; S. Imada; S. Saito

The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a V/sub cc/ of 4 V at 85 degrees C. >


IEEE Journal of Solid-state Circuits | 2012

A 151mm 2 64Gb MLC NAND flash memory in 24nm CMOS technology

Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Takeshi Ogawa; Toshiaki Edahiro; Makoto Iwai; Osamu Nagao; Junji Musha; Takatoshi Minamoto; Yuka Furuta; Kosuke Yanagidaira; Yuya Suzuki; Dai Nakamura; Yoshikazu Hosomura; Rieko Tanaka; Mai Muramoto; Go Shikata; Ayako Yuminaka; Kiyofumi Sakurai; Manabu Sakai; Mitsuyuki Watanabe; Yosuke Kato; Toru Miwa

A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the chip size, 2-physical-plane configuration with 16 KB wordline-length, a new bit-line hook-up architecture, and a top-metal-congestion-free optimized peripheral circuit floor plan, are introduced. As a result, 151 mm2 die size with an excellent 79% cell area efficiency is achieved. Newly introduced precharge detect algorithm and smart precharge algorithm improve program throughput by 10%. 14 MB/s program throughput is obtained, which is comparable or even higher performance than NAND flash memories reported in the previous 30 nm technology generation. The proposed smart precharge algorithm reduces program operation current by 6%, and 25 mA operation current with 16 KB programming is achieved. Moreover, a high-speed asynchronous DDR interface is incorporated and 266 MB/s data transfer is achieved.

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