Hitoshi Shiga

A CMOS bandgap reference circuit with sub-1-V operation

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the sum of the built-in voltage of the diode V/sub f/ and the thermal voltage V/sub T/ of kT/q multiplied by a constant. Therefore, V/sub ref/ is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V/sub ref/ has been converted from the sum of two currents; one is proportional to V/sub f/ and the other is proportional to V/sub T/. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-/spl mu/m flash memory process. Measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.

A CMOS band-gap reference circuit with sub 1 V operation

This paper proposes a CMOS band-gap reference (BGR) circuit, which can successfully operate with sub-1 V. In the conventional BGR circuit, the output voltage, Vref, is the sum of the built-in voltage of the diode, Vf, and the thermal voltage, VT, of kT/q multiplied by a constant. Thereby, Vref is about 1.25 V, which limits a low Vcc operation below 1 V. Conversely, in the proposed BGR circuit, Vref has been converted from the sum of two currents; one is proportional to Vf; and the other is proportional to VT. An experimental BGR circuit, which is simply composed of a CMOS opamp, diodes, and resistors, has been fabricated in a conventional double metal 0.4 /spl mu/m process. Measured Vref is 515 mV/spl plusmn/15 mV (3 /spl sigma/) for 23 samples on the same wafer at 27/spl deg/C through 125/spl deg/C.

A 56-nm CMOS 99-

A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed. This is the worlds first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum2 per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size

{\hbox {mm}}^{2}

Fabricated in 56nm CMOS technology, an 8Gb multi-level NAND Flash memory occupies 98.8mm2, with a memory cell size of 0.0075mum/b. The 10MB/s programming and 93ms block copy are also realized by introducing 8kB page, noise-cancellation circuits, external page copy and the dual VDD scheme enabling efficient use of 1MB blocks

8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

A 1.8 V-only 32 Mb NOR flash EEPROM uses a channel-erasing scheme for the 0.49 /spl mu/m/sup 2/ cell in 0.25 /spl mu/m CMOS technology. The block decoder circuit with an erase-reset sequence performs channel-erase. The bit line direct sense permits sub-1.8 V operation, suitable for use in handheld systems.A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput

A low-power wordline voltage generating system is developed for low-voltage flash memories. The limit for the stand-by current including the operation current for the band-gap reference and the stand-by wordline voltage generator is discussed. The system was implemented on a 1.8-V 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and achieved with very low stand-by current of 2 /spl mu/A typically, and high operating frequency of 25 MHz in read operation at 1.8 V. A low-voltage level shifter with high-speed switching is also proposed.

A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme

NAND flash memories are used in digital still cameras, cellular phones, MP3 players and various memory cards. As seen in the growing needs for applications such as solid-state drives and video camcoders, the market demands for larger-capacity storage has continuously increased and NAND Flash memories are enabling a wide range of new applications. In such situations, to achieve larger capacity at low cost per bit, technical improvement in feature-size scaling [1], multi-bit per cell [2,3] and area reduction are essential.

Wordline voltage generating system for low-power low-voltage flash memories

Combining a negative-gate channel-erasing NOR flash memory technology with an aggressively-scaled NAND flash process technology results in a 64 Mb NOR flash memory with 0.27 /spl mu/m/sup 2/ cell and 44 mm/sup 2/ chip. The flash memory provides 4 independent banks for flexible dual operation and unique block redundancy for yield.

A 113mm2 32Gb 3b/cell NAND flash memory

NAND flash memories are now indispensable for our modern lives. The application range of the storage memory devices began with digital still cameras and has been extended to USB memories, memory cards, MP3 players, cell phones including smart phones, netbooks, and so on. This is because higher storage capacity and lower cost are realized through means of technology scaling every year. Emerging markets, such as solid-state drives (SSDs) and data-storage servers, require lower bit cost, higher program and read throughputs, and lower power consumption

A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the chip size, 2-physical-plane configuration with 16 KB wordline-length, a new bit-line hook-up architecture, and a top-metal-congestion-free optimized peripheral circuit floor plan, are introduced. As a result, 151 mm2 die size with an excellent 79% cell area efficiency is achieved. Newly introduced precharge detect algorithm and smart precharge algorithm improve program throughput by 10%. 14 MB/s program throughput is obtained, which is comparable or even higher performance than NAND flash memories reported in the previous 30 nm technology generation. The proposed smart precharge algorithm reduces program operation current by 6%, and 25 mA operation current with 16 KB programming is achieved. Moreover, a high-speed asynchronous DDR interface is incorporated and 266 MB/s data transfer is achieved.