Satoru Takase

A 500-megabyte/s data-rate 4.5 M DRAM

A 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was achieved by designing a DRAM core with a very high internal column bandwidth, and coupling this core with a block-oriented, small-swing, synchronous interface that uses skew-canceling clocks. The DRAM has a 1-kbyte*2-line sense-amp cache and is assembled in a 32-pin vertical surface-mount-type plastic package. The measurement results clearly verified the 500-Mbyte/s data rate. >

A 130.7mm 2 2-layer 32Gb ReRAM memory device in 24nm technology

ReRAM has been considered as one of the potential technologies for the next-generation nonvolatile memory, given its fast access speed, high reliability, and multi-level capability. Multiple-layered architectures have been used for several megabit test-chips and memory macros [1-3]. This paper presents a MeOx-based 32Gb ReRAM test chip developed in 24nm technology.

A 130.7-

A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit area overhead. Die efficiency is further improved by sharing wordlines and bitlines between adjacent blocks. As the number of sense amplifiers under the memory array is limited, a pipelined array control scheme is adopted to compensate the performance impact while utilizing the fast switching time of ReRAM cells. With the chip current consumption being dominated by the array leakage and sensitive to array bias and operating conditions, a charge pump stage control scheme is introduced to dynamically adapt to the operating conditions for optimal power consumption. Smart Read during sensing and leakage current compensation scheme during programming are applied to the large-block architecture and achieve a chip density that is several orders of magnitude higher than prior ReRAM developments.

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This DRAM features (1) interleaved operation of 16 dependent banks with 1.6 GB/s data rate, (2) flexible mapping redundancy which suits multi-bank memory, and (3) additional-refresh that realizes a low data retention power DRAM.

2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

A novel 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate has been designed. This high data-rate has been achieved by coupling a very high internal column bandwidth DRAM core with a very high internal column bandwidth, and coupling this core with a block oriented, small-swing, synchronous interface that uses skew canceling clocks. The DRAM has a 1-kbyte*2 line sense amplifier cache. This DRAM is assembled in a 32-pin vertical surface mount type plastic package.<<ETX>>

A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme

This DRAM realizes multiple-bank performance with small area overhead by sharing data transmission circuitry among all banks, and minimizes the time and the cost required to produce cut-down products. To enhance cost-efficiency, 2 page sizes are offered in one chip, ensuring suitability for widespread use: 1 kB for low-end computers requiring low power consumption and 2 kB for high-end workstations. This 288 Mb RDRAM contains four 72 Mb quadrants, in the center of which row decoders (XDECs) are located horizontally. Column decoders (YDECs) are at the edge of each quadrant near the chip center. For the 2/spl times/16 split, dependent bank, bank0 through bank15 and bank16 through bank31 function the same as the dependent bank. Bank15 and bank16 are, however, independent of each other. The same bank resides in 2 quadrants positioned diagonally. Both leftand right-hand halves (36 Mb units) of each quadrant contain 16 banks which are arranged as 16 vertical strips. In each unit, sense amplifiers (SAs) are shared between adjacent strips. 34 global bank-select-lines (GBSLs) corresponding to the vertical rows of SAs and 36 Main DQ Lines (MDQs) run horizontally over the array in half of each quadrant divided by XDECs along with column-select-lines (CSLs). MDQs are connected to the second sense amplifiers (SSAs) placed vertically at the chip center and shared between the left- and right-hand halves of the chip. Beside the SSAs, the shift registers (SRs) for 8 to 1 parallel-serial conversion are arranged vertically and transfer 144b to 18 I/O pads every column access.