Kiyomi Naruke

Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness

The effects of thinning the FLOTEX EEPROM tunnel oxide on its reliability are investigated using capacitors and cell structures with oxide thickness ranging from 47 to 100 AA. A low-electric-field oxide leakage current is induced by charge injection stressing, and it increases with decreasing oxide thickness. Its conduction mechanism is found to be different from that caused by positive charge accumulation in that it has the opposite thickness dependence. A corresponding increase of charge loss in a write/erase (W/E)-cycled EEPROM cell is observed with decreasing oxide thickness in a room-temperature retention test. When oxide thickness is decreased, the maximum number of W/E cycles to tunnel-oxide breakdown decreases with the decrease in charge to breakdown of the negatively biased gate. For scaling down the EEPROM tunnel oxide, the most serious limiting factor is oxide leakage current induced by W/E cycling stress, resulting in data-retention degradation.<<ETX>>

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6- mu m triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0*1.8 mu m/sup 2/ has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11*6.95 mm/sup 2/, and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm/sup 2/ by using the minimal cell size (2.0*10 mu m/sup 2/). >

A new flash-erase EEPROM cell with a sidewall select-gate on its source side

A novel flash-erase EEPROM (electrically erasable PROM) cell is described. It consists of a stacked-gate MOSFET with a sidewall select gate on the source side of the FET (SISOS cell). Three layers of polysilicon are used. The cell has a self-aligned structure which makes it possible to realize a small cell area of 4.0*3.5 mu m/sup 2/ with 1.0- mu m technology. It also has a select gate which prevents undesirable leakage current due to overerasing. The cell is programmed by channel hot electron injection at the source side and erased by Fowler-Nordheim tunneling of electrons from the floating gate to the drain. The programming by source-side injection makes it possible for the drain junction to be optimized independently of hot electron generation and for the erasure to be achieved with no degradation in programmability.<<ETX>>

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation

A 16-Mb flash EEPROM has been developed based on the 0.6-/spl mu/m triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 /spl mu/m/spl times/1.7 /spl mu/m, resulting in a die size of 7.7 mm/spl times/17.32 mm. >

The study of the thermal oxide films on silicon wafers by Fourier transform infrared attenuated total reflection spectroscopy

Fourier transform infrared attenuated total reflectance technique was used to measure the SiOH and SiH contents in the thermal oxide films grown on Si wafers. It was found that the SiOH groups in the bulk could be eliminated by annealing at 850 °C, whereas SiOH at the Si/SiO2 interface could only be removed by annealing at 1000 °C. It was also found that SiOH and SiH groups were generated in the thin oxide film by γ‐ray irradiation. The presence of H or H2 in SiO2 is necessary to explain the result.

A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

Combining a negative-gate channel-erasing NOR flash memory technology with an aggressively-scaled NAND flash process technology results in a 64 Mb NOR flash memory with 0.27 /spl mu/m/sup 2/ cell and 44 mm/sup 2/ chip. The flash memory provides 4 independent banks for flexible dual operation and unique block redundancy for yield.

A 5 V-only 0.6 mu m flash EEPROM with row decoder scheme in triple-well structure

An experimental 4-Mb flash EEPROM realizes 5-V-only operation by introducing a compact row decoder with a triple-well structure. Since the cell-source voltage during erase is only 5 V, high source-junction breakdown voltage is not necessary, making a smaller cell feasible. By optimizing memory cell implant, fast programming is achieved with 5 V drain voltage. A simple stable EEPROM redundancy circuit reduces chip test cost and has minimum effect on chip size compared with a polysilicon redundancy circuit. The chip is packaged in a 48-spin cerdip.<<ETX>>

A 151mm 2 64Gb MLC NAND flash memory in 24nm CMOS technology

NAND flash memories are now indispensable for our modern lives. The application range of the storage memory devices began with digital still cameras and has been extended to USB memories, memory cards, MP3 players, cell phones including smart phones, netbooks, and so on. This is because higher storage capacity and lower cost are realized through means of technology scaling every year. Emerging markets, such as solid-state drives (SSDs) and data-storage servers, require lower bit cost, higher program and read throughputs, and lower power consumption

A 151-mm

A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the chip size, 2-physical-plane configuration with 16 KB wordline-length, a new bit-line hook-up architecture, and a top-metal-congestion-free optimized peripheral circuit floor plan, are introduced. As a result, 151 mm2 die size with an excellent 79% cell area efficiency is achieved. Newly introduced precharge detect algorithm and smart precharge algorithm improve program throughput by 10%. 14 MB/s program throughput is obtained, which is comparable or even higher performance than NAND flash memories reported in the previous 30 nm technology generation. The proposed smart precharge algorithm reduces program operation current by 6%, and 25 mA operation current with 16 KB programming is achieved. Moreover, a high-speed asynchronous DDR interface is incorporated and 266 MB/s data transfer is achieved.

^{2}

A modified Inpact-Ionlzatlon Reconblnation(IR) nodel is proposed to explain oxlde danage under dynanlc stress. The stress apptied to the tunnel oxide of an EEPROM is not D.C. but A.C. equivalent current. According to coventional theory, the oxlde tifetlne depends on electric fietdtll t2l. However, experlments on EEPROMs do not indlcate any such clear dependence. In the nodlfted IR nodel, trapped holes and free holes ln the oxlde are dealt with separately, and the tlrift of holes ln the oxlde valence band is considered. Thls nodel allows the experinental results to be explained.