Hironori Banba

A CMOS bandgap reference circuit with sub-1-V operation

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the sum of the built-in voltage of the diode V/sub f/ and the thermal voltage V/sub T/ of kT/q multiplied by a constant. Therefore, V/sub ref/ is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V/sub ref/ has been converted from the sum of two currents; one is proportional to V/sub f/ and the other is proportional to V/sub T/. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-/spl mu/m flash memory process. Measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6- mu m triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0*1.8 mu m/sup 2/ has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11*6.95 mm/sup 2/, and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm/sup 2/ by using the minimal cell size (2.0*10 mu m/sup 2/). >

A CMOS band-gap reference circuit with sub 1 V operation

This paper proposes a CMOS band-gap reference (BGR) circuit, which can successfully operate with sub-1 V. In the conventional BGR circuit, the output voltage, Vref, is the sum of the built-in voltage of the diode, Vf, and the thermal voltage, VT, of kT/q multiplied by a constant. Thereby, Vref is about 1.25 V, which limits a low Vcc operation below 1 V. Conversely, in the proposed BGR circuit, Vref has been converted from the sum of two currents; one is proportional to Vf; and the other is proportional to VT. An experimental BGR circuit, which is simply composed of a CMOS opamp, diodes, and resistors, has been fabricated in a conventional double metal 0.4 /spl mu/m process. Measured Vref is 515 mV/spl plusmn/15 mV (3 /spl sigma/) for 23 samples on the same wafer at 27/spl deg/C through 125/spl deg/C.

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation

A 16-Mb flash EEPROM has been developed based on the 0.6-/spl mu/m triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 /spl mu/m/spl times/1.7 /spl mu/m, resulting in a die size of 7.7 mm/spl times/17.32 mm. >

Wordline voltage generating system for low-power low-voltage flash memories

A low-power wordline voltage generating system is developed for low-voltage flash memories. The limit for the stand-by current including the operation current for the band-gap reference and the stand-by wordline voltage generator is discussed. The system was implemented on a 1.8-V 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and achieved with very low stand-by current of 2 /spl mu/A typically, and high operating frequency of 25 MHz in read operation at 1.8 V. A low-voltage level shifter with high-speed switching is also proposed.

A 5 V-only 0.6 mu m flash EEPROM with row decoder scheme in triple-well structure

An experimental 4-Mb flash EEPROM realizes 5-V-only operation by introducing a compact row decoder with a triple-well structure. Since the cell-source voltage during erase is only 5 V, high source-junction breakdown voltage is not necessary, making a smaller cell feasible. By optimizing memory cell implant, fast programming is achieved with 5 V drain voltage. A simple stable EEPROM redundancy circuit reduces chip test cost and has minimum effect on chip size compared with a polysilicon redundancy circuit. The chip is packaged in a 48-spin cerdip.<<ETX>>

A 3.3 V-only 16 Mb flash memory with row-decoding scheme

A 3.3 V only 16 M flash memory with a row decoding scheme is fabricated in 0.4 /spl mu/m double-well double-metal CMOS. Negative-gate-biased erase enables 3.3 V-only operation, and a double-word-line structure with second aluminum minimizes word-line delay. Row redundancy with self-convergence improves yield. Quasi-differential sensing with address transition detection gives fast random access.