Shigeru Atsumi

A CMOS bandgap reference circuit with sub-1-V operation

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the sum of the built-in voltage of the diode V/sub f/ and the thermal voltage V/sub T/ of kT/q multiplied by a constant. Therefore, V/sub ref/ is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V/sub ref/ has been converted from the sum of two currents; one is proportional to V/sub f/ and the other is proportional to V/sub T/. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-/spl mu/m flash memory process. Measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6- mu m triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0*1.8 mu m/sup 2/ has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11*6.95 mm/sup 2/, and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm/sup 2/ by using the minimal cell size (2.0*10 mu m/sup 2/). >

A CMOS band-gap reference circuit with sub 1 V operation

This paper proposes a CMOS band-gap reference (BGR) circuit, which can successfully operate with sub-1 V. In the conventional BGR circuit, the output voltage, Vref, is the sum of the built-in voltage of the diode, Vf, and the thermal voltage, VT, of kT/q multiplied by a constant. Thereby, Vref is about 1.25 V, which limits a low Vcc operation below 1 V. Conversely, in the proposed BGR circuit, Vref has been converted from the sum of two currents; one is proportional to Vf; and the other is proportional to VT. An experimental BGR circuit, which is simply composed of a CMOS opamp, diodes, and resistors, has been fabricated in a conventional double metal 0.4 /spl mu/m process. Measured Vref is 515 mV/spl plusmn/15 mV (3 /spl sigma/) for 23 samples on the same wafer at 27/spl deg/C through 125/spl deg/C.

Optimization of word-line booster circuits for low-voltage flash memories

Two word-line booster circuits, which output a word-line voltage for reading dash memory data, are analyzed and optimized. A capacitor-switched booster circuit outputs a voltage higher than the supply voltage by switching the connection state of one of more boosting capacitors with the load capacitor from parallel to series. The optimum number of capacitors and capacitance per boosting capacitor are obtained as a function of the voltage ratio of the required high voltage to the supply voltage. The operation current consumed by the boosting operation is also analytically derived. In addition, another booster circuit-Dickson charge-pump circuit-is optimized under the condition to maximize the output current at a high word-line voltage. Characteristics of the booster circuits are compared, and the selection of booster circuit for low-voltage flash memory is discussed.

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation

A 16-Mb flash EEPROM has been developed based on the 0.6-/spl mu/m triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 /spl mu/m/spl times/1.7 /spl mu/m, resulting in a die size of 7.7 mm/spl times/17.32 mm. >

Design of a sense circuit for low-voltage flash memories

A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and successfully operated at a low voltage of 1.5 V.

A 4-Mbit CMOS EPROM

A high-density (512K-word/spl times/8-b) erasable programmable read-only memory (EPROM) has been designed and fabricated by using 0.8-/spl mu/m n-well CMOS technology. A novel chip layout and a sense-amplifier circuit produce a 120-ns access time and a 4-mA operational supply current. The interpoly dielectric, composed of a triple-layer structure, realizes a 10-/spl mu/s/byte fast programming time, in spite of scaling the programming voltage V/SUB PP/ from 12.5 V for a 1-Mb EPROM to 10.5 V for this 4-Mb EPROM. To meet the increasing demand for a one-time programmable (OTP) ROM, a circuit is implemented to monitor the access time after the assembly. A novel redundancy scheme is incorporated to reduce additional tests after the laser fuse programming. Cell size and chip size are 3.1/spl times/2.9 /spl mu/m/SUP 2/ and 5.86/spl times/14.92 mm/SUP 2/, respectively.

A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme

A 1.8 V-only 32 Mb NOR flash EEPROM uses a channel-erasing scheme for the 0.49 /spl mu/m/sup 2/ cell in 0.25 /spl mu/m CMOS technology. The block decoder circuit with an erase-reset sequence performs channel-erase. The bit line direct sense permits sub-1.8 V operation, suitable for use in handheld systems.A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.

Wordline voltage generating system for low-power low-voltage flash memories

A low-power wordline voltage generating system is developed for low-voltage flash memories. The limit for the stand-by current including the operation current for the band-gap reference and the stand-by wordline voltage generator is discussed. The system was implemented on a 1.8-V 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and achieved with very low stand-by current of 2 /spl mu/A typically, and high operating frequency of 25 MHz in read operation at 1.8 V. A low-voltage level shifter with high-speed switching is also proposed.

A programmable 80ns 1Mb CMOS EPROM

CONTINUING DEMANDS for high-speed, low-power and highdensity EPROMs are being created by the evolution of high performance computer systems. This paper will describe an asynchronous lMb CMOS EPROM with both word and byte operation modes’. An Address Transition Detector (.4TD), MidWord-Line Buffer (MWLB) and sensing are utilized to realize an 80ns access time. Programming of 2Ops/word has been realized by introducing selective DSA (Diffused Self-Align) structure into the memory cell transistor. The CMOS circuit and automatic power down function result in 50mW operating power and subPW standby power.