Kiyoshi Mitani

Causes and Prevention of Temperature-Dependent Bubbles in Silicon Wafer Bonding

Unbonded areas or bubbles generated at the interface of bonded silicon wafers in the temperature range of 200-800°C have been investigated. Experiments described in this paper demonstrate that the desorption of hydrocarbon contamination at the silicon wafer surfaces appears to be a necessary condition for the formation of these bubbles. SIMS data also indicate the existence of hydrocarbons at the bonding interface. It is speculated that hydrocarbon gas such as CH4 is required for bubble nucleation and that either CH4 or H2 itself or a mixture of both gases is contained in these bubbles. Finally, methods to prevent the formation of these bubbles are presented.

Bubble-Free Wafer Bonding of GaAs and InP on Silicon in a Microcleanroom

A technology is presented that will allow the fabrication of thin III-V compound semiconductor layers of low dislocation density on silicon substrates. GaAs and InP wafers were successfully bonded to bare and oxidized silicon substrates in an experimental setup that produces a microcleanroom for bubble-free bonding in any environment. The bonding strength was found to be comparable to that of Si on oxidized Si and sufficient to subsequent grinding and polishing of the bonded wafers.

Wafer bonding technology for silicon-on-insulator applications: a review

School of Engineering, Duke University, Durham, North Carolina, 27706. The status of wafer bonding technology especially for silicon-on-insulator (SOI) materials is reviewed. General advantages of wafer bonding as well as specific problems of wafer bonding, such as interface bubble formation, and solutions for these problems are discussed. The specific requirements for SOI materials in terms of SOI layer thickness and the appropriate thinning procedures are dealt with. Interface properties such as bonding strength and electrical properties are also reviewed. Various device results are mentioned.

A New Evaluation Method of Silicon Wafer Bonding Interfaces and Bonding Strength by KOH Etching

KOH anisotropic etching is used to study the interfaces of bonded silicon wafers. This method has been developed to detect the presence of bubbles or unbonded areas with a gap of less than 0.27 µm, which is the detection limit of an IR camera. Because of the anisotropic etching properties of KOH and the presence of interfacial oxide layers, the etching surface morphology is dependent on the crystallographic orientation of the cross section. Correlation of etching results to the bonding strength of silicon wafers with and without a thermally oxidized silicon layer is also discussed.

Bubble formation during silicon wafer bonding: causes and remedies

Several causes of bubble formation are reported. The role of surface contamination and methods of reducing bubble formation are discussed. In the experiments unstructured, polished single-crystal silicon wafers are used although for actual micromechanical applications, wafers with grooved surfaces frequently have to be bonded. Problems associated with wafer flatness, trapped air, and particles are considered and solutions proposed. The remaining problem of bubble formation in an intermediate temperature range is also discussed. It is proposed that the cause of wafer bonding bubbles formed during annealing is the presence of hydrocarbons contaminating silicon surfaces. Bubbles are generated when hydrocarbons are evaporated from the surface in the 200-800 degrees C temperature range. At higher temperatures, bubbles are dissolved into the bulk silicon or interface oxide layers. There are two different bubble sizes. The large one may be deducted by infrared, whereas the smaller one requires the use of X-ray topography. Preheating wafers at 600-800 degrees C prior to bonding can evaporate all the absorbed hydrocarbons on the surface and prevent bubble formation after bonding and annealing.<<ETX>>

Study of HF Defects in Thin, Bonded Silicon-on-Insulator Dependent on Original Wafers

To study the origin of HF defects in thin, bonded silicon-on-insulator (SOI) wafers fabricated by the plasma assisted chemical etching (PACE) process, the dependence of HF defects on original wafers [wafers fabricated by Czochralski method (CZ wafers), hydrogen-annealed CZ wafers and epitaxial wafers] was investigated. It was shown that HF defect density was affected by the type of original wafer used, and no HF defect was detected when epitaxial wafers were used as bond wafers. HF defects were detected on 0.2 µm or thinner SOI wafers with CZ wafers. Crystal originated particles (COPs) at SOI and buried oxide (SOI/BOX) interface were found to be the main origin of HF defects by inspecting light point defects (LPDs) at the SOI/BOX interface.

Deposition and Properties of Polycrystalline Si for Solar Cells

A tin coated graphite substrate was used for growing polycrystalline Si layers by CVD in the SiCl4–H2 system. A mean grain size of poly-Si layers on the tin coated substrate was 50–100 µm, compared with several microns on an uncoated substrate. Moreover the tin intermediate layer seems to play an important role to make a flat surface. The crystalline size could be further enlarged to 100–500 µm by introduction of melting process before normal CVD. A Schottky barrier solar cell using those poly-Si layers showed the open-circuit voltage of 0.25 V, the shortcircuit current density of 12.8 mA/cm2, fill factor of 59% and conversion efficiency of 2.0% under the solar intensity of 92.8 mW/cm2.

Heavy-Metal (Fe/Ni/Cu) Behavior in Ultrathin Bonded Silicon-On-Insulator (SOI) Wafers Evaluated Using Radioactive Isotope Tracers

The behavior of Fe, Ni and Cu in bonded silicon-on-insulator (SOI) wafers thinned down to 0.5 µm by plasma-assisted chemical etching (PACE) was investigated for the first time by the radioactive isotope tracer method, which can avoid the evaluation errors due to contamination during sample preparation or analysis. When ultrathin bonded SOI wafers without an intentional gettering site were contaminated with Fe or Ni from the surface, Fe and Ni did not diffuse into the substrate through the buried oxide (BOX) layer after annealing in N2(2%O2) ambient at 900°C and 700°C, respectively. Cu easily diffused into the substrate through the BOX layer after annealing at 700°C for 60 min, and was captured at the bonding interface. It was found that the behavior of Ni, which exhibits the same diffusivity in Si as does Cu, was quite different in ultrathin bonded SOI wafers from that in bulk Si wafers due to the BOX layer of the SOI structure.

Detection of Particles on Quarter µm Thick or Thinner SOI Wafers

It was shown that as a probe for a particle detection system based on the principle of light scattering a 430 nm laser was effective for detecting particles on thin silicon on insulator (SOI) wafers. In particular, a p-polarized oblique incident light beam was more effective than that at normal incidence. This laser was suitable for an SOI structure of down to 0.2 µm SOI layer and 0.2 µm buried oxide (BOX) layer. In addition, it is predicted in terms of the reflectivity of a 430 nm laser that there are the suitable BOX thicknesses in SOI structure of less than 0.1 µm SOI layer thickness.

Effective KOH Etching Prior to Modified Secco Etching for Analyzing Defects in Thin Bonded Silicon on Insulator (SOI) Wafers

The modified Secco etching which was developed for detecting threading dislocations in separation by implanted oxygen (SIMOX) wafers showed etch pits with a density of 103–106/ cm2 when it was applied to bonded silicon on insulator (SOI) wafers thinner than 1 µ m produced by the plasma assisted chemical etching (PACE) process including touch polishing. When these pits were observed, a group of pits appeared as a scratch pattern. Also the density of pits was dependent on the remaining SOI thickness after the first diluted Secco etching in the modified Secco etching process. These results indicated that the density of defects had a certain distribution in the SOI thickness direction and that the defects were different from threading dislocations which reached buried oxides from the surface. In order to observe the distribution of defect density in the SOI depth direction, KOH etching was utilized prior to the modified Secco etching. Using this method, it was found that surface defects were predominant and bulk defects were also present in thin bonded SOI layers.