Toshiaki Iwamatsu

Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 /spl mu/m era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-relate speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk structure. Moreover, it is shown that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSIs. It is concluded that SOI technology with HTI structure is one of the solutions against the scaling limitations.

16 Mb DRAM/SOI technologies for sub-1 V operation

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFETs, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16 MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1 V.

Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.

Suppression of delay time instability on frequency using field shield isolation technology for deep sub-micron SOI circuits

It was demonstrated that Field Shield (FS) isolation technology can suppress the delay time instability depending on operating frequency. FS isolation technology has been proposed to tie the body potential without any area penalties in gate array. Moreover, the effect of body resistance on the instability was also investigated using device simulation.

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

We achieved 135 GHz f/sub max/ and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of V/sub th/ variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

A 0.18 /spl mu/m silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated. The hybrid trench isolation is a combination of partial trench isolation and full trench isolation. In the partial trench isolation region, a part of the SOI layer remains under the field oxide so as to provide scalable body-tied SOI metal-oxide-semiconductor field-effect transistors (MOSFETs), while in the full trench isolation region, the whole of the SOI layer is replaced by the field oxide so as to provide high quality passives. It is demonstrated that this technology improves the maximum oscillation frequency and the minimum noise figure of the MOSFET and the Q-factor of the inductor, compared with bulk technology. Moreover, it is verified that the partial-trench-isolated body-tied structure suppresses the floating body effect of SOI devices for RF/analog applications and thus guarantees low-noise characteristics, stability, linearity, and reliability. It is concluded that this technology will be one of the key technologies for supporting the evolution of wireless communications.

Approaches to extra low voltage DRAM operation by SOI-DRAM

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-/spl mu/m 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.

Analysis of delay time instability according to the operating frequency in field shield isolated SOI circuits

It has been demonstrated that field shield (FS) isolation technology can suppress the delay time instability according to the operating frequency. The FS isolation technology has been proposed to fix the body potential without any area penalty in a gate array. In this technology, an FS plate, which is an additional polysilicon gate, is introduced to electrically isolate active regions. The body potential of the SOI MOSFET can be fixed through the SOI layer under the FS plate. The effect of body resistance on the delay time instability was also investigated using device simulation. The simulation showed that although the body potential momentarily falls to a nonsteady level due to capacitive coupling during switching operation, the body potential recovers to a steady level, following the RC law. From the simulation result, a helpful design guideline concerning the body resistance was deduced. This guideline showed that the FS isolation has a superior capability to suppress the frequency-dependent instability for practical deep submicron SOI circuits.

Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs

Transient drain currents caused by proton microprobe irradiations in partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) were analyzed for soft-error issues. Transient currents of the body-tied MOSFETs can be lowered compared to those of the floating body SOI MOSFETs by suppression of the floating body effect. The effectiveness of the body-tie structure was analyzed by device simulation. Increase in the body potential by proton irradiation is suppressed efficiently in the narrow-channel body-tied SOI MOSFETs due to the low body resistance to excess carrier extraction. On the other hand, the body potential of narrow-channel floating body SOI MOSFETs increase to higher levels than those of the wide-channel MOSFETs due to the lower body capacitance. It is indicated that narrow-channel body-tied SOI MOSFETs are suitable for highly reliable devices. Moreover, a more reliable body-tied structure with high impurity concentration in the body regions to reduce the body resistance in the structure is proposed. The collected drain charge was able to be reduced by utilizing this structure. These devices are expected to be applied to highly reliable LSIs used for satellite systems, server and mainstream LSI applications of the multimedia era.

Bulk-layout-compatible 0.18-/spl mu/m SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

Partial-trench-isolated (PTI) 0.18-/spl mu/m SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM were obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint.