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Dive into the research topics where Hideki Naruoka is active.

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Featured researches published by Hideki Naruoka.


Journal of Applied Physics | 2005

Vacancy-type defects in strained-Si layers deposited on SiGe∕Si structures probed by using monoenergetic positron beams

Akira Uedono; Nobuyoshi Hattori; Hideki Naruoka; Shoji Ishibashi; Ryoichi Suzuki; Toshiyuki Ohdaira

Vacancy-type defects in strained-Si layers deposited on Si0.75Ge0.25∕graded-SiGe∕Si structures were probed by using monoenergetic positron beams. The Doppler broadening spectra of the annihilation radiation and the lifetime spectra of the positrons were measured for samples before and after annealing (800–1050 °C). For an as-received sample, the defects in the strained-Si layer were identified as vacancy-type defects coupled with Ge. The mean open size of these defects was estimated to be close to that of a divacancy. The line-shape parameter, S, corresponding to the positron annihilation in the strained-Si layers decreased with increasing annealing temperature, but no large change in the positron lifetime was observed. From a comparison between the Doppler broadening profiles for the strained-Si films and those calculated using the projector augmented-wave method, it was found that the number of Ge atoms forming a complex by coupling with a defect increased with increasing annealing temperature. The numb...


IEEE Electron Device Letters | 2002

Preliminary study of a novel scanning charge-pumping method using extra gates for SOI wafer inspection

Haruhiko Yoshida; Toshinori Takami; Takayuki Uchihashi; Seigô Kishino; Hideki Naruoka; Yoji Mashiko

A novel scanning charge-pumping method using one or more extra contactless gates is proposed for silicon-on-insulator (SOI) wafer inspection. In the proposed method, a contactless; gate electrode is used as a measuring gate instead of the permanent gate electrode of normal metal-oxide-semiconductor transistors, allowing a wafer map of interface trap density to be obtained. A preliminary study is carried out using a sample device having two extra gate electrodes in the close vicinity of a measuring gate electrode, which are contacted on an oxidized SOI wafer. The results demonstrate that the proposed method is a promising technique for the characterization of interface trap density in SOI wafers.


Archive | 2002

Method for treating substrates for microelectronics and substrates obtained by said method

Thierry Barge; Bruno Ghyselen; Toshiaki Iwamatsu; Hideki Naruoka; Junichiro Furihata; Kiyoshi Mitani


Archive | 2003

Semiconductor substrate with stacked oxide and SOI layers with a molten or epitaxial layer formed on an edge of the stacked layers

Yoshiko Yoshida; Hideki Naruoka; Yasuhiro Kimura; Yasuo Yamaguchi; Toshiaki Iwamatsu; Yuuichi Hirano


Archive | 2000

Method for treating substrates for microelectronics

Thierry Barge; Bruno Ghyselen; Toshiaki Iwamatsu; Hideki Naruoka; Junichiro Furihata; Kiyoshi Mitani


The Japan Society of Applied Physics | 2002

Effective Metal Gettering Technique using Polysilicon Substrate Contact Structure for SOI Devices

Hideki Naruoka; Toshiaki Iwamatsu; Takashi Ipposhi; Nobuyoshi Hattori; Yasuo Inoue; Yoji Mashiko


The Japan Society of Applied Physics | 2001

A Highly Reliable 0.18 μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide

Shigenobu Maeda; K. Shiga; Hideki Naruoka; Nobuyoshi Hattori; Toshiaki Iwamatsu; Takuji Matsumoto; Yuuichi Hirano; Yasuo Yamaguchi; Takashi Ipposhi; Shigeto Maegawa; M. Inuishi


Archive | 2001

Halbleitervorrichtung und Herstellungsverfahren der Halbleitervorrichtung A semiconductor device and manufacturing method of the semiconductor device

Toshiaki Iwamatsu; Takashi Ipposhi; Hideki Naruoka; Nobuyoshi Hattori; Shigeto Maegawa; Yasuo Yamaguchi; Takuji Matsumoto


Archive | 2000

Verfahren zur behandlung eines halbleitersubstrats

Thierry Barge; Bruno Ghyselen; Toshiaki Iwamatsu; Hideki Naruoka; Junichiro Furihata; Kiyoshi Mitani


Archive | 2000

Verfahren zur behandlung eines halbleitersubstrats A process for treating a semiconductor substrate

Thierry Barge; Bruno Ghyselen; Toshiaki Iwamatsu; Hideki Naruoka; Junichiro Furihata; Kiyoshi Mitani

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Junichiro Furihata

East Tennessee State University

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