Kiyoshi Takeuchi

Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation

A simple model is proposed, which is able to calculate V/sub TH/ standard deviation due to random dopant placement in the channel, for arbitrary vertical impurity distributions. Substantial decrease in V/sub TH/ fluctuation, while keeping V/sub TH/ the same, is confirmed for low surface impurity channel MOSFETs, in agreement with the model prediction.

Sub-10-nm planar-bulk-CMOS devices using lateral junction control

Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were observed for n/pMOSFETs with the gate length of 5 nm at 0.4 V for the first time.

45-nm gate length CMOS technology and beyond using steep halo

45-nm CMOS devices with a steep halo using a high-ramp-rate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 /spl mu/A//spl mu/m for an off current less than 10 nA//spl mu/m at 1.2 V. For an off current less than 300 nA//spl mu/m, 33-nm pMOSFETs have a high drive current of 403 /spl mu/A//spl mu/m at 1.2 V. In order to fabricate a steeper halo than these MOSFETs, a source/drain extension (SDE) activation using the HRR-SA process was performed after a deep source/drain (S/D) formation. By using this sequence defined as a reverse-order S/D formation, 24-nm nMOSFETs are achieved with a high drive current of 796 /spl mu/A//spl mu/m for an off current less than 300 nA//spl mu/m at 1.2 V.

An effective channel length determination method for LDD MOSFETs

We propose a definition of MOSFET effective channel length (L/sub EFF/), that provides a method of determining L/sub EFF/ as a constant, and external resistance (R/sub EXT/) virtually as a constant, even for lightly doped drain (LDD) transistors. A unified relationship between this L/sub EFF/ and MOSFET drive current (linear and saturation) that is common to a wide range of drain structures was confirmed. Therefore, the L/sub EFF/ is useful, not only for compact analytical models, but also as an index of MOSFET performance applicable to both single drain and LDD devices. The dependence of the channel length on the source/drain structure was clarified by introducing the concept of local contribution to channel length. The L/sub EFF/ varies, even if the metallurgical channel length is fixed, depending on the design of the source/drain.

Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOS

A new raised source/drain (RSD) structure is proposed, which combines facet controlled in-situ-doped selective Si epitaxial growth (SEG) and solid-phase diffusion (SPD). This can provide ultra-shallow junctions without sacrificing the parasitic resistance or capacitance. 0.1 /spl mu/m pMOSFETs with 20 nm deep junctions exhibiting excellent electrical characteristics and reliability were demonstrated. CMOS process compatibility was also confirmed.

Effects of the velocity saturated region on MOSFET characteristics

A simple, accurate and universal relationship between MOSFET drain current in saturation, effective channel length, and gate drive has been found. It can be explained by a simple analytical model, whose validity is supported by numerical simulation. The model shows that the length of a velocity saturated region is a crucial parameter for describing MOSFET performance, particularly for short channel devices. The shrinkage of the length deteriorates the merit of channel length scaling. >

Practical finFET design considering GIDL for LSTP (low standby power) devices

Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization of lateral spread and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10nm fin width

High performance sub-tenth micron CMOS using advanced boron doping and WSi/sub 2/ dual gate process

High performance sub-tenth micron CMOS, exhibiting a record ring oscillator delay of 13.6 ps at 1.5 V, has been fabricated. Solid-phase diffusion from BSG was successfully utilized in CMOS fabrication for shallow p/sup +/ junction formation. To eliminate reverse short channel effect and improve punch-through immunity of nMOS, a channel implantation after source/drain activation method was used. Combining these techniques, high speed CMOS operation at 0.07 /spl mu/m with acceptable stand-by leakage was obtained. WSi/sub 2//poly dual gate process without extra mask steps is also demonstrated.

SRAM critical yield evaluation based on comprehensive physical / statistical modeling, considering anomalous non-Gaussian intrinsic transistor fluctuations

Critical SRAM yield evaluation/analysis for more robust design optimizations against variation is presented based on comprehensive physical modeling and statistical analysis of transistor intrinsic fluctuations for 65 nm-node and beyond MOSFETs. Predictive atomistic-3D-TCAD simulations reveal the origins of the non-Gaussian Vth-distribution that causes large sigmaVth deviation from the Pelgrom-relationship for specific small gate length devices. By using realistic statistical compact-modeling and fast Monte Carlo circuit simulations, it was demonstrated that the appropriate cell-design recognizing the anomalous sigmaVth enables to rescue significant possible yield loss caused by the particular behaviors of the intrinsic transistor fluctuations.

A new effective channel length determination method for LDD MOSFETs

A novel effective channel length (L/sub eff/) determination method applicable to LDD (lightly doped drain) MOSFETs is described. The new L/sub eff/, which is determined as a constant that minimizes bias-dependent dispersion of external resistance, is suited for representing device performance, both in linear and saturation regions. In addition, the bias-dependent L/sub eff/ previously proposed is discussed and compared with metallurgical channel length. The idea of a local contribution factor to effective channel length is presented for analysis of these methods.<<ETX>>