Masayasu Tanaka

HiSIM: a MOSFET model for circuit simulation connecting circuit performance with technology

Circuit simulation models should be pragmatic, but should be accurate at the same time. HiSIM (Hiroshima-University STARC IGFET Model), aiming to fulfil both requirements, is based on an iterative surface-potential determination in 2D device simulators. However, the essence of each technology is extracted from measurements, thus simplifying modeling procedure and allowing large-scale circuit simulation with 0.1 /spl mu/m-MOSFET technologies.

Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation

A new threshold voltage (V/sub th/) model has been developed for the pocket-implant technology. The model extracts the threshold condition from the entire mobile charge concentration in the channel with only five additional parameters; the maximum doping concentration (N/sub subp/) of the pocket profile, the penetration length (L/sub p/) into the channel, and three enhanced short-channel parameters. The model reproduces the measured V/sub th/ versus. gate-length (L/sub gate/) characteristics with an average error of a few millivolts under any bias conditions.

Validity of mobility universality for scaled metal–oxide–semiconductor field-effect transistors down to 100 nm gate length

Mobility universality, confirmed for long-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), is demonstrated to be preserved for scaled MOSFET technologies down to 100 nm gate length, although phenomena such as quantum-mechanical and poly-silicon depletion effects play important roles. This result was obtained by applying a compact model based on the drift-diffusion approximation and relying only on Ids–Vgs measurements instead of using a conventional method with supplemental Cgate–Vgs measurements. It is confirmed that the carrier mobility is still governed by the electric field applied, and that the drift-diffusion approximation remains valid down to channel length of 100 nm. Consequently, the carrier behavior of such scaled small-size MOSFETs can be precisely described by simple analytical equations, which is important for the development of efficient circuit-simulation models.

A Self-Consistent Non-Quasi-Static MOSFET Model for Circuit Simulation Based on Transient Carrier Response

We have developed a basic concept for a non-quasi-static (NQS) metal-oxide-semiconductor field-effect transistor (MOSFET) model for circuit simulation. The model is based on a carrier-response delay, and incorporates the time and position dependence of the carrier density along the channel. This is the exact origin of the NQS effect. By comparing model results with 2D device simulation results, solving the continuity equation explicitly, we found that the carrier-response delay consisted of a conductive delay and a charging delay. The developed model was successfully applied to test transient behavior of the drain current.

A practical small-signal equivalent circuit model for RF-MOSFETs valid up to the cut-off frequency

The non-quasistatic contribution to the Y-parameters is shown to be much smaller than usually expected. This is especially true for advanced pocket-implant MOSFET technologies being developed for RF devices. Therefore, a simple and practical equivalent-circuit model valid up to the cut-off frequency becomes possible. The small interdependence of the different model elements allows an explicit and sequential extraction of the individual element values.

Model of Pocket-Implant Mosfets for Circuit Simulation

A new threshold voltage (Vth) model has been developed for the pocket-implant technology. The model extracts the threshold condition from the entire mobile charge concentration in the channel with only two parameters; the maximum doping concentration (N su h p ) of the pocket profile and the penetration length (L o ) into the channel. The model reproduces the measured Vth vs. gate-length (Lgate) characteristics with an average error of a few mV under any bias conditions.

High-Electric-Field Electron Transport at Silicon/Silicon-Dioxide Interface Inversion Layer

A time-of-flight experiment is performed to directly measure the properties of high-tangential-electric-field electron transport at the inversion layer in a metal oxide semiconductor device. We have observed that the saturation velocity is about 6.5×106 cm/s. The structure of the device used for the time-of-flight experiment is not identical to a conventional metal oxide semiconductor field-effect transistor. We found that the measured electron mobility is higher than that for the conventional metal oxide semiconductor field-effect transistor at the same effective normal electric field. Our results further elucidate the properties of electron mobility more than the reported results of Cooper and Nelsons experiment.

Circuit-simulation model of gate-drain-capacitance changes in small-size MOSFETs due to high channel-field gradients

The field gradient along the MOSFET channel is included in the modeling of the gate-drain capacitance (C/sub gd/) by an induced capacitance approach. The new approach has been successfully implemented in surface-potential based model HiSIM (Hiroshima-university STARC IGFET Model) and is capable of reproducing measured effects, which are particularly significant for pocket-implant technology, accurately.

Formation of Nickel Self-Aligned Silicide by Using Cyclic Deposition Method

We have developed a novel nickel self-aligned silicide (salicide) process for future scaled metal-oxide-semiconductor field-effect transistors (MOS-FETs). Ni/Si multi-layered structures were fabricated by the cyclic deposition of Ni and Si. Nickel monosilicide (NiSi) films with a low resistivity, a uniform thickness, and a good morphology were obtained on Si(100) substrates after annealing at 400–600°C. Nickel silicide formed on SiO2 can be removed by wet etching if the total atomic number ratio of Ni to Si in the deposited layers is larger than unity. This shows that the nickel salicide process is possible by our method. We have fabricated MOS-FET structures with NiSi and confirmed that the consumption of Si in the substrate is much lower in our method than in the conventional method.

Carrier transport in highly generated carrier concentration

We have investigated photo-generated carrier transport (photocurrent) in the p–n junction experimentally and theoretically. The photocurrent was measured with various laser-pulse intensities under different reverse bias conditions applied at the p–n junction. For a low laser intensity, the measured photocurrent maintains the same shape as the irradiated laser pulse with diminished time delay. Increasing the laser intensity, however, transport delay of the measured photocurrent is observed with broadened pulse shapes, especially under weak bias conditions. This broadened photocurrent shape could not be reproduced by conventional two-dimensional (2D) device simulations, which solve the basic device equations. Under highly generated carrier concentration, it is demonstrated here that the carrier transport is mostly governed by non-equilibrium carrier dynamics, which is not included in the conventional device equations.