Kiyoyuki Morita

Si nanofabrication using AFM field enhanced oxidation and anisotropic wet chemical etching

Abstract We present a novel Si nanofabrication method based on an atomic force microscope (AFM) field-enhanced oxidation and an anisotropic wet chemical etching using SIMOX (separation by implanted oxygen) wafer. A newly developed AFM system enables this fabrication method to be fully compatible with a conventional VLSI process. Using this technique, Si quantum wire with a feature size of 60 nm has been successfully fabricated within the intended area. Moreover, by means of a structural analysis by cross-sectional transmission electron microscopy, it is confirmed that the AFM-field-enhanced oxide film has a similar excellent structure as thermally grown oxide.

Fabrication and Transport Properties of Silicon Quantum Wire Gate-All-Around Transistor

A novel fabrication method of silicon quantum wire gate-all-around transistor (GAAT), in which the gate oxide and the gate electrode are wrapped around ultrafine silicon quantum wire, has been proposed. In order to verify one-dimensional (1D) subband effects, we have studied quantum transport in Si quantum wire GAAT with a width of 50 nm at 1.5 K in zero-magnetic field and in fields up to 10 T. Electrical population and magnetic depopulation of 1D subbands are clearly observed.

Electrical Switching Phenomena in a Phase Change Material in Contact with Metallic Nanowires

We observed electrical switching phenomena in a phase change material (Ge2Sb2Te5) in contact with metallic nanowires of 100 nm, which were embedded in a track-etched polycarbonate membrane by electroplating. While the electrical resistance of the system did not change when applied voltage was 0–1 V, switching occurred from a high-resistance state (HS) to a low-resistance state (LS) when voltage was increased from 0 V to 5 V and then decreased to 0 V. The maximum current was 100 nA. LS was 10 times more conductive than HS. A reset operation from LS to HS was realized using a 20 ns pulse of 5 V. Switchings from HS to LS and from LS to HS were confirmed several times, demonstrating that the device is rewriteable.

Stochastic associative processor operated by random voltages

The latest LSIs still lack performance in pattern matching and picture recognition. Living organisms, on the other hand, devote very little energy to processing of this type, suggesting that they operate according to a fundamentally different concept. There is a notable difference between the two types of processing: the most similar pattern is always chosen by the conventional digital pattern matching process, whereas the choice made by an organism is not always the same: both the most similar patterns and other similar patterns are also chosen stochastically. To realize processing of this latter type, we examined a calculation method for stochastically selecting memorized patterns that show greater similar to the input pattern. Specifically, by the use of a random voltage sequence, we executed stochastic calculation and examined to what extent the accuracy of the solution is improved by increasing the number of random voltage sequences. Although calculation of the Manhattan distance cannot be realized by simply applying stochastic computing, it can be done stochastically by inputting the same random voltage sequence to two modules synchronously. We also found that the accuracy of the solution is improved by increasing the number of random voltage sequences. This processor operates so efficiently that the power consumption for calculation does not increase in proportion to the number of memorized vector elements. This characteristic is equivalent to a higher accuracy being obtained by a smaller number of random voltage sequences: a very promising characteristic of a stochastic associative processor.

Novel Fabrication Method of Si Nanostructures Using Atomic Force Microscope (AFM) Field-Enhanced Oxidation and Anisotropic Wet Chemical Etching

We have demonstrated a novel method of fabricating Si nanostructures. Based on a combination of atomic force microscope (AFM) field-enhanced oxidation and anisotropic wet chemical etching, Si nanostructures with a minimum width of 50 nm are successfully obtained within the intended area with precise alignment. Overlay patterning followed by AFM field-enhanced oxidation is carried out with high accuracy. It is confirmed that the field-enhanced oxide line with a thickness of at least about 3 nm can act as an mask against anisotropic wet chemical etching. This method enables the realization of sub-10 nm Si nanostructures.

A Novel Negative Voltage Generator Circuit: Application of a Ferroelectric Capacitor to Low-Power LSIs

In this paper, a novel voltage generator circuit using a ferroelectric capacitor is described. This circuit consists of two metal-oxide-semiconductor (MOS) transistors, a ferroelectric capacitor and a dielectric capacitor, which can convert a positive input voltage into a negative output voltage. We describe in detail the design and operation principles of the circuit. We have demonstrated the expected circuit operation and evaluated its performance characteristics such as voltage efficiency and verified, using an experimental circuit, that a negative voltage is continuously generated. The magnitude of the measured output voltage value was smaller than that of the simulation result, possibly due to the existence of parasitic resistance in the experimental circuit. The simulation results suggest that our circuit is suitable for reducing the standby leakage current of MOS transistors, one of the most serious power consumption-related problems in advanced CMOS LSIs.

Reduction of Leakage Current by HfO 2 High K Dielectric Film Stacked on the Ferroelectric Layer of a MFIS Structure

We report here the reduction of leakage current through a thin ferroelectric layer by insertion of an HfO 2 film. We fabricated metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) and metal-ferroelectric-insulator-metal (MFIS) structures. A Pb x La 1 m x TiO 3 (PLT) ferroelectric layer was deposited on a thermally oxidized p-type Si substrate with a Zr buffer layer. Adopting an HfO 2 layer on the ferroelectric layer of a MIFIS structure with an equivalent oxide thickness (EOT) of 5 nm resulted in a reduction by only 13 percent of the voltage distribution on the ferroelectric layer. Applying HfO 2 to the ferroelectric layer of a MFIS structure, however, led to a 70% decrease in leakage current: from 2.7 2 10 m 8 to 0.76 2 10 m 8 A/cm 2 at +1 V. An HfO 2 film, by itself, shows leakage that is 3 orders of magnitude smaller than that of PLT; clearly, insertion of the film impedes leakage through the ferroelectric layer. This characteristic is believed to contribute to extension of the retention time of MFMIS FETs.

Novel diffusion control process using ultra thin buffer layer for MFIS memory

Abstract MFIS structures having excellent clear interfaces and well-crystallized ferroelectric layer were successfully fabricated by a newly developed ultra thin metal buffer layer process on SiO2/Si. We examined the effect of sputtered Zr or ZrO2 ultra thin films as a buffer layer for PbxLa1−xTiO3 (PLT) growth. TEM observation revealed that the buffer layer formation process in which Zr oxidized after the metal deposition had advantages to produce MFIS structures. This method is also superior for the crystallization and the control of the orientation of PLT thin film on amorphous SiO2. Especially, for buffer layer thicknesses below 10 nm, preferred c-axis oriented PLT thin films were grown. The I-V characteristics of MFIS-FET fabricated by the proposed method showed a clear memory window due to the remanent polarization of the ferroelectric thin film. This process is the most attractive candidate for realizing MFIS structure memory.