Kjetil Svarstad

Assertion based verification using PSL-like properties in Haskell

With the increasing complexity of designs, the verification costs grow considerably. Using Assertion Based Verification with assertions implemented on real hardware, can speed up the verification process. Property Specification Language is one of the common standards for describing formal properties and specifications of a design. We implemented a subset of PSL operations in Haskell in this work. A functional programming language like Haskell can appear as an advantageous choice for formal verification and high-level descriptions. We use the implemented PSL operators to set up different synthesizable PSL properties. The implemented PSL operators are tested on an FPGA for an AMBA AHB-based system which is also implemented in Haskell.

An area efficient hardware architecture design for H.264/AVC intra prediction reconstruction path based on partial reconfiguration

The H.264/AVC standard supports intra prediction in order to reduce spatial redundancy in the video frame. The intra prediction process for one macro block requires reconstructing the left and top neighbor macro blocks where the reconstruction path includes a number of processing units such as integer transform, quantization, inverse quantization and inverse integer transform. In order to meet the real time performance constraints of different video standards, a high throughput through this path is necessary. In this paper we propose architecture for real time implementation of the reconstruction path used in the H.264/AVC where the hardware is designed to be used as part of a complete H.264 video coding system. Each processing block executes in a single clock cycle for all calculations required for one 4×4 block. In order to minimize area cost while maintaining the performance, dynamic partial reconfiguration is employed in the quantization and inverse quantization modules such that an area - efficient solution is found without impairing the throughput.

A high-throughput and low-complexity H.264/AVC intra 16×16 prediction architecture for HD video sequences

Intra prediction reduces redundancy by exploiting the similarities between video samples within one video frame and it is characterized by high data dependency, high number of memory accesses and intensive computational complexity. This paper proposes a high-throughput and low-complexity intra 16×16 prediction architecture that supports H.264/AVC high profile. The high speed prediction for H.264 meets the requirement for real time encoding of HD sequences. The architecture is capable of processing all four prediction modes, including highly complex plane mode. Parallel processing of 16 pixels, corresponding to the 4×4 block, is employed. The design is able to encode entire macroblock within 48 cycles. The proposed architecture is synthesized and implemented on Kintex 705 - XC7K325T board and requires 94 MHz to encode 4k×2k at 60 fps in real time.

A low complexity H.264/AVC 4×4 intra prediction architecture with macroblock/block reordering

The H.264/AVC standard possesses high complexity features, among which intra prediction characterized by high data dependency and immense amount of computation. Therefore the compression in real time represents a challenge. This paper presents a novel low-complexity architecture of intra 4×4 prediction for baseline, main and high profiles H.264 frame encoders that meet different throughput requirements. Intra 4×4 prediction consists of a prediction and a reconstruction loop, and these two phases are performed in a pipeline manner by processing sixteen data items in parallel. A new macroblock level scanning order is proposed in order to increase efficiency and exploit the data dependency between blocks. Number of scenarios, such as on fly processing of macroblock rows and simultaneous processing of several macroblock rows, have been exploited depending on the input buffer capabilities. The second case requires input buffer that accommodates a number of macroblocks that correspond to the frame width. Ultra high throughput requires parallel processing of large amount of data. For proposed waveform macroblock scanning order, the intra prediction module can be used a processing element for building a complex reconfigurable design. By varying number of intra prediction modules, design can be adapted to achieve different throughput. The focus of this paper is on the architecture of the intra prediction module. In the case of on fly processing, it takes 48 cycles to process one macroblock (MB). This proposed architecture is synthesized and implemented on Kintex 705-XC7K325T board and requires 48 MHz to encode 4k×2k at 30 fps in real time, which is significant reduction of frequency requirement compared to the state of the art.

System-level modelling of dynamic reconfigurable designs using functional programming abstractions

With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.

An adaptive high-throughput edge detection filtering system using dynamic partial reconfiguration

This paper proposes an architecture consisting of various edge detection filters implemented on modern FPGA platforms exploiting a feature of dynamic partial reconfiguration (DPR). The developed system targets small-scale systems, and its use in the educational setting can be of great interest. Two-dimensional convolution is the most common operation in digital video/image processing, and its implementation is highly demanding in terms of computational intensity, high throughput and hardware resources. In the case of a variety of filtering techniques used for edge detection, the hardware resources become a constraint, in particular when using convolution kernels with varying parameters and sizes. DPR introduces significant functional density and increased flexibility by providing logic switching within a constrained hardware area. Furthermore, parallel and pipelined hardware solutions for filter implementation overcome computational performance of software solutions and increase effectiveness compared to static hardware solution. The advantages of accommodating a number of various algorithms within the same datapath at low cost and considerable time are exploited in the proposed work. The effectiveness of the DPR feature for edge detection application is tested on the filter scenarios varying in sizes, complexity and intensity of computation, where the resource utilization and timing are evaluated. Experimental results are proposed through comparisons between different configurations (with DPR and without DPR) and detailed performance analysis.

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.

The European Masters in Embedded Computing Systems (EMECS)

The European Masters in Embedded Computing Systems (EMECS) is a joint masters programme from the Technical University of Kaiserslautern, the Norwegian University of Science and Technology and the University of Southampton. The programme has run since 2010 and the European Union has recently renewed funding until 2020. EMECS has been very successful, thanks to a number of unique features. Four cohorts of international students have graduated from the programme with 100% employment at the end. This paper describes the features of the programme to date and our plans to enhance the programme in the future.

An MPEG-2 to H.264/AVC intra-frame transcoder architecture with mode decision in transform domain

The computational complexity of the MPEG-2 to H.264/AVC transcoder, in particular the encoder, is technically challenging, but it can be reduced by reusing the information accessible in the decoding process. A low-latency mode decision algorithm performed in transform domain within the MPEG-2 decoder is proposed. The encoder stage contains two mutually exclusive intra prediction algorithms of block sizes 4x4 and 16x16 sharing the hardware logic. The shared intra prediction unit is supported by an on-chip memory organization. The proposed architecture is implemented on FPGA development board. Its implementation supports high throughputs that correspond to a real-time processing of a variety of video resolutions including QFHD 2160p at 30 fps. Furthermore, the minimal required frequency for CIF, SD and HD1080p resolutions are significantly reduced compared to the state of the art1.

Synthesizable assertion checkers in high levels of abstraction

Verification is a challenge that consumes an increasing part of the design time in the design flow of modern hardware systems. We propose an Assertion Based Verification (ABV) method with embedding synthesizable clock-accurate assertion checkers in higher levels of abstraction in the design flow. Both the Design Under Verification (DUV) and its synthesizable assertion checkers are described using the same language which leads to an easier integration of the checkers. Using this approach on a case study confirms its feasibility without any penalty in the working frequency with less than 5% increased area consumption on a Kintex7 FPGA.