Gottfried Beer

Embedded wafer level ball grid array (eWLB) technology for system integration

Silicon front-end and assembly and packaging technology more and more merge. In addition interconnect density reaches limits for advanced CMOS technology. In this paper we introduce the fan-out embedded wafer level packaging technology, which is an example to link front-end and packaging technology and offers additional freedom for interconnect design. We demonstrate capabilites for system integration of the eWLB technology, which includes system on chip (SoC) integration and system in package (SiP) integration like side by side and stacking of devices. We highlight the importance of understanding properties of new materials, which influence warpage or heat dissipation. We also show the excellent performance of the eWLB package for mm-wave applications.

A digital CMOS DNA chip

A fully electronic medium density DNA micro array is presented using a CMOS process extended by gold electrodes. The chip provides 128 sensor sites, in-sensor site current-mode A/D conversion, peripheral circuitry including bandgap and current references, D/A-converters to provide electrode bias voltages, calibration circuitry, and a 6 pin interface for power supply and serial digital data transfer.

Integrated circuits for the biology-to-silicon interface

An overview is given of CMOS-based sensor and actuator chips for in-vitro applications in the biotechnology area. We address the challenges and the potential of the combination of solid-state circuits with the wet world of bio molecules and living cells. Basic biological operating principles, market considerations, extended CMOS processing issues, and concrete circuit examples are discussed.

3D eWLB — Horizontal and vertical interconnects for integration of passive components

In this paper, we present simulation and measurement results of single-ended and differential vertical interconnections realized using the thin-film redistribution layer (RDL) and through encapsulant vias (TEVs) of the embedded wafer level ball grid array (eWLB) package. We demonstrate that the fan-out area of the eWLB can be used advantageous for the design of passive devices using TEV structures. We show simulation and measurement results of inductors and transformers built up by RDL and TEV structures. Thus, these structures are designed in the fan-out volume of the eWLB mold compound. We discuss the electrical performance of the 3D interconnections and embedded passives realized using TEVs. The presented examples demonstrate that the eWLB technology is an attractive candidate for system integration because this technology enables the design of 2D passives in RDL and 3D passives using RDL and TEV.

An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS Technology

A 0.13μm CMOS chip is fabricated with eight resonator-amplifiers to demonstrate a highly integrated gravimetric sensor based on an FBAR oscillator. The oscillator is attached via flip-chip bonding to a CMOS resonator. Each active 1.86GHz oscillator draws 27mA from a single 17V supply for 200×200μm2 sensors. The resonance frequency shifts by 5MHz in ethanol and 7.3MHz in water and jitter is <3kHz

CMOS-Based Biosensor Arrays

CMOS-based sensor array chips provide new and attractive features as compared to todays standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

A novel 3D packaging concept for RF powered sensor grains

We present a novel three-dimensional (3D) embedded wafer-level ball grid array (eWLB) system in package (SiP) solution for biochips and micro labs. This 3D SiP includes three major components, a complementary metal oxide semiconductor (CMOS)-tunnel magneto resistance (TMR) sensor biochip for magnetic bead-sensing stacked on a radio frequency identification (RFID) microchip and a 13.56 MHz coil antenna for wireless energy and data transfer. The power supply and the serial peripheral interface (SPI) chip interconnections between the CMOS-TMR sensor biochip (slave) and the RFID microchip (master) are implemented with a novel embedded Z-line (EZL) vertical contact technology through the mold compound. The 13.56 MHz antenna is embedded into the fan-out area of the bottom redistribution layer of the eWLB. With this setup we are able to maximize the RFID reading distance and to ensure a displacement to the TMR sensor surface. We achieve an overall volume of the 3D SiP of only 5.6 mm × 3.6 mm × 0.7 mm applying the eWLB technology. Due to the RFID technology the developed 3D SiP does not need any external contacts and cabling. Therefore it can be encapsulated into harsh environments. In addition the top fan-out surface of the eWLB can be used for adhesive bonding to higher level analyzing setups. The results demonstrate that innovative SiP technology using the eWLB technology combined with chip and antenna design allow to realize modern subsystems e.g. for medical applications.

A secure miniaturized wireless sensor node for a smart home demonstrator

Recently, the technology of wireless sensor networks (WSNs) experiences a growing use in home automation or advanced industry infrastructure applications. Despite a strong interest of industries in this technology, key issues like miniaturization and security of WSN nodes has not been solved yet. State-of-the-art WSN nodes do not provide credible security nor satisfying configurability and miniaturized implementations. This publication deals with these limitations and presents a WSN node that provides security, configurability, and a miniaturized design. To show the sensor node feasibility, the WSN node is implemented within a smart home demonstrator. Additionally, a miniaturized pre-study WSN node design is presented using the novel embedded wafer level ball grid array (eWLB) packaging technology. Furthermore, an eWLB based WSN node design is proposed that further miniaturize the presented WSN node.

Novel embedded Z line (EZL) vertical interconnect technology for eWLB

In this paper, we present the novel embedded Z line (EZL) interconnection technology, which allows fabricating vertical contacts in the embedded wafer level ball grid array (eWLB) package. The presented solution enables the realization of vertical interconnections and passive components of wide range of widths and pitches and high metal-pattern resolution. We discuss the electrical characteristics of interconnections and high-frequency transitions realized using EZLs and compare them to structures realized using through encapsulant vias (TEVs) and through silicon vias (TSVs). We show examples of high-density EZL daisy chain structure and 3D package for RF-powered sensor with EZL interconnections to demonstrate the feasibility of the EZL technology. We present the concept of vertical antenna integration using EZL and show measurement results of a vertical EZL dipole antenna integrated in an eWLB package to demonstrate the flexibility and millimeter-wave capabilities of the EZL technology. The presented examples demonstrate that the new EZL technology is competitive to both TEV and TSV interconnect options and that it is particularly interesting for systems combining RF/high-speed and power devices.

Interconnect technologies for system-in-package integration

Heterogeneous system integration is a powerful approach to combine chips and components from different technologies into highly functional products with small form factors. Interconnect technologies are key to any such integration concepts. Because of the increasing challenge of cost efficiency, appropriate system-in-package (SiP) platform technologies are required that offer flexible use based upon processing options and modular production capabilities. Today, typical interconnects in a SiP toolbox are new technologies like redistribution layers (RDLs), 3D thru-silicon vias (TSVs) and 3D thru-encapsulant vias (TEVs) in addition to innovative variations of flip-chip bonding, wire bonding, and several options for die attach. Such interconnects enable the 3D integration of stacked or embedded chips and other components like passives, shielding or antennas. Scaling trends in component density (Moores law) and computing efficiency (Koomeys law) allow circuit miniaturization and increased functionality of logic ICs, but also drive the necessary number of external input/output pins of the packaged system (Rents rule). Often, this results in small ball pitch dimensions enabled by usage of high-density BGA substrates or fan-out packages with adequate redistribution layers. Moreover, increasing power densities demand efficient thermal coupling between chip, package, and board. Heat dissipation has become an important topic for both logic and power semiconductors systems. In this paper, main highperformance interconnect technologies are discussed. In a first example, we discuss the interconnect capabilities of the very thin (~ 0.3 mm) TSLP package platform meanwhile in mass production for various designs. We especially highlight the embedded Wafer Level Ball Grid Array (eWLB) technology, an example for a highly flexible system integration platform. Similarly, the new Blade technology of Infineon offers important advantages for power semiconductor systems by means of low parasitic interconnects and redistribution capability.