Klaus Schuegraf

Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks

S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled FinFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in FinFET devices for the 22nm node and remain effective with conservative scaling of contact / gate CD only.

Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology

FinFET technology is prone to suffer from line edge roughness (LER)-based VT variation with scaling. It also lacks a simple implementation of multiple VT technology needed for power management. To address these challenges, in this paper we present an epitaxially defined FinFET (EDFinFET) as an alternate to FinFET architecture for nodes 15 nm and beyond. We show by statistical simulations that EDFinFET reduces overall VT variability with an 80% reduction in LER-based variability in comparison with FinFETs. We present dynamic threshold MOS (DTMOS) configuration of EDFinFET using the available body terminal to individual transistors. The DTMOS configuration reduces LER-based variability by 90% and overall variability by 59%. It also has excellent subthreshold slope (SS) and gives 43% higher ION compared with FinFETs. Meanwhile, EDFinFET shows poorer SS and lower ION than FinFET due to single gate control. However, it is capable of multiple VT, which leads to circuit level power optimization.

Integrated circuits: Memory grows up

Three-dimensional integration may allow for continued improvements in the speed, density and cost of non-volatile memory.

Epitaxialy defined (ED) FinFET: to reduce V T variability and enable multiple V T

Device variability has become a major concern for CMOS technology [1]. Various sources of variability include Random Dopant Fluctuation (RDF), Gate Edge Roughness (GER) and Line Edge Roughness (LER) [2]. The introduction of FinFETs at 22nm node has two issues. Firstly, the effect of RDF is considerably reduced due to undoped fins [3]. But the aggressive fin width (Wfin) requirement (~Lg/3 [4]) to reduce short channel effect aggravates the electrical impact of LER and makes it greatest contributor to patterning induced variability [2]. Moreover, the edge roughness does not scale with technology and remains independent of the type of lithography used [5]. Secondly, multiple threshold voltage (VT) is achieved in planar technology by various patterned implant steps, which is unavailable for FinFET technology as the fin is undoped. Multiple VT transistor technology is essential for power vs. performance optimization by circuit designers [6]. In this work, we propose an alternative to conventional FinFET structure which can (a) reduce overall variability by 4× reduction in sensitivity to LER and (b) enable multiple VT by applying body bias dynamically without any costly patterned implant steps.

Epi defined (ED) FinFET: An alternate device architecture for high mobility Ge channel integration in PMOSFET

Band to band tunneling (BTBT) is a major challenge in Ge FinFETs due to its smaller band gap. Narrow fin widths reduce BTBT due to quantum confinement (QC). However, Line Edge Roughness (LER) on narrower fins causes large VT variability. Previously, we have proposed an architecture named Epitaxially Defined (ED) FinFET to reduce VT variability due to LER wherein channel depletion is defined by low doped highly uniform epitaxy (thus named Epi Defined FinFET) (epi-thickness non uniformity<;2%) over a thick highly doped Si fin instead of lithography based patterning subject to LER (non-uniformity<;50% i.e. 2nm LER on a 4nm fin). In the present work, we propose integration of Ge into EDFinFET architecture in which Ge (or SiGe) is grown on top of Si fin. Proposed structure shows 10× reduction in LER based VT variability in comparison to FinFETs. Valence band QC in gate oxide/Ge/Si stack is used to control BTBT. Biaxial stress in thin Ge epitaxially grown on Si results in 27% higher ION. Thin Ge film required is lower than critical defect free thickness of Ge epitaxy on Si. Hence defect free Ge integration into FinFET architecture in enabled. We also show that EDFinFET can enable multiple VT just by the application of a bias at the body terminal.

Textured AZO on silicon oxy-nitride barrier films for enhanced light trapping in micromorph tandem junction solar cells

Aluminum doped Zinc Oxide (AZO) films have been reported as the transparent front contact layer in single and tandem junction thin film silicon solar cells. AZO films form highly transparent and conductive layers on glass surfaces with the possibility of further enhancement of solar cell performance by light trapping through wet-chemical texturing of the AZO surface. However, most reports have demonstrated such AZO films either on alumino-borosilicate glasses which are prohibitively expensive for low cost solar modules, or on commercial glass with barrier films deposited by other deposition methods.

Memory grows up: Integrated circuits

Three-dimensional integration may allow for continued improvements in the speed, density and cost of non-volatile memory.