Kohei Sugihara

Numerical analysis of single photon detection avalanche photodiodes operated in the Geiger mode

For a wide range of the thicknesses of the charge and the multiplication layers, detection efficiency and dark count probability are numerically investigated for GaInAs∕InP single photon detection avalanche photodiodes (APD’s) which are operated in the Geiger mode. Breakdown probability and dark currents are calculated to evaluate detection efficiency and dark count probability. The result shows that dark count probability can be significantly reduced by increasing the thickness of the charge layer, whereas detection efficiency is expected to decline steeply at some thickness of the charge layer. Moreover, increasing the thickness of the multiplication layer does not continue to reduce dark count probability, which increases when the multiplication layer is thicker than a critical thickness. Finally, we show a design guideline of single photon detection APD’s with higher detection efficiency and lower dark count probability.

Drivability improvement on deep-submicron MOSFETs by elevation of source/drain regions

Deep submicron MOSFETs with elevated source/drain (S/D) structures, where S/D extension regions were partially elevated besides deep S/D regions, were fabricated by use of Si selective epitaxial growth technique. As fairly compared with a well-developed conventional MOSFET, we clarify an advantage of the elevated S/D structures, i.e., improvement upon driving performance with keeping excellent short-channel characteristics, which is enhanced for decrease in gate sidewall spacer width. The experimental results are explained in terms of the reduction in S/D parasitic resistance by addition of the Si epitaxial layer where the impurity profile is suitable.

Parasitic Resistance Reduction in Deep Submicron Dual-Gate Transistors with Partially Elevated Source/Drain Extension Regions Fabricated by Complementary Metal-Oxide-Semiconductor Technologies

Deep submicron dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with partially elevated source/drain (S/D) structures were fabricated using complementary MOS (CMOS) technologies. In comparison with well-defined conventional MOSFETs, it is revealed that the drivability is appreciably enhanced by the S/D elevation and, further, that a p-channel MOSFET gains more from the S/D elevation than an n-channel MOSFET. Investigation of the parasitic resistance is consistent with the results of the transistor characteristics.

Advantage of Shallow Trench Isolation over Local Oxidation of Silicon on Alignment Tolerance

We investigate the differences between the breakdown characteristics against contact hole etching for shallow trench isolation (STI) and the local oxidation of silicon (LOCOS). Although the breakdown voltage of STI varied negligibly despite the large contact overlap, the isolation characteristics of the LOCOS were drastically degraded due to the slight overlapping with the contact hole. The cross-sectional scanning electron microscope observations revealed that the considerable difference between STI and the LOCOS is closely related to the field oxide shapes modified by contact hole etching. We concluded that STI, in which the original field oxide abruptly projects above the substrate surface, has an advantage over the LOCOS not only against isolation space reduction but also alignment tolerance reduction.

Planar Avalanche Photodiode for Long-Haul Single-Photon Optic Fiber Communications

We present a high-performance planar GaInAs/InP avalanche photodiode (APD) for long-haul single-photon optic fiber communications, that is, quantum cryptography. The APDs for single-photon communications require a high single-photon detection efficiency (ηdet) relating to bitrate and a low ratio of dark count probability (Pdc) to ηdet limiting communication distance. We fabricated the APD with the combination of a long multiplication region length and a low carrier sheet density on the basis of numerical analysis. The Pdc/ηdet monotonically decreased with operation temperature lowered, and the ratio reached 5.9 ×10-6 with the ηdet of 13% at 77 K. The Pdc was 7.7 ×10-7, which corresponds to a dark count rate of 0.38 kHz. The useful APD and the effective layer design are reported.

Improvement of Surface Morphology of Epitaxial Silicon Film for Elevated Source/Drain Ultrathin Silicon-on-Insulator Complementary-Metal-Oxide-Semiconductor Devices

A novel selective epitaxial growth (SEG) technology which uses ultrahigh-vacuum chemical vapor deposition and low-damage sidewall etching with a Cl2-plasma gas is experimentally demonstrated for elevated source/drain (S/D) ultrathin silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) devices. It is found that the deviation of parasitic S/D series resistance in elevated S/D sub-40-nm-thick SOI metal-oxide-semiconductor field-effect transistors (MOSFETs) can be nearly as low as that in bulk MOSFETs, because the excellent surface morphology of the epitaxial Si layer enables formation of a uniform CoSi2 film. Moreover, neither gate/drain bridging nor any other leakage phenomena are pronounced. These results indicate that this SEG technology is promising for elevated S/D ultrathin SOI CMOS devices for the 90-nm technology node and beyond.

Epitaxial Si1−x Gex grown into fine contact hole by ultrahigh-vacuum chemical vapor deposition

Abstract An ultrahigh-vacuum chemical vapor deposition technique with disilane (Si 2 H 6 ) and germane (GeH 4 ) molecular flux is applied to Si 1− x Ge x ( x =0–0.15) selective growth into fine contact holes. The growth behavior of epitaxial Si 1− x Ge x layer is influenced by addition of GeH 4 with Si 2 H 6 flow rate kept at constant, which is interpreted by estimation of facet growth rates. The growth rates of (311) and (111) facets are drastically decreased by addition of a small amount of GeH 4 . As a result, in the fine holes, the epitaxial layer height of Si 1− x Ge x is limited by the (311) growth rate and decreased compared with pure Si.

Improvement of alignment tolerance against contact hole etching by growing of underlying silicon-selective epitaxial layer

Abstract We demonstrated that the influences of a contact hole overlapping a local oxidation of silicon (LOCOS) isolation can be reduced by using selective epitaxial growth, which is improved the alignment margin of the contact hole in the LOCOS region. The experimental results indicated that the epitaxial layer underlying the contact bottoms prevented the TiSi2 layer from penetrating into the Si substrate. Therefore, the leakage current at the overlapping region was drastically suppressed for a configuration where the contact hole and the LOCOS region overlapped. The breakdown voltage was improved compared with a case without an epitaxial layer.

A Dual-Gate Complementary Metal-Oxide-Semiconductor Technology with Novel Self-Aligned Pocket Implantation which Takes Advantage of Elevated Source/Drain Configurations

A dual-gate complementary metal-oxide-semiconductor technology with novel self-aligned pocket implantation is demonstrated which takes advantage of the elevated source/drain (S/D) configurations. Using the present procedure, S/D junction capacitance and leakage current were significantly suppressed for p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) as well as for n-channel MOSFETs without degradation of the short channel characteristics. These results are interpreted in terms of the fact that the pocket impurity profiles shift to the upper positions in the deep S/D regions, though the impurity distribution at the gate edges was hardly varied. Furthermore, the suppression effects were more marked for a higher pocket implantation dosage, which will be required to suppress the short channel effects in future MOSFETs. In addition, improvement of drivability due to the reduction of the parasitic S/D resistance, an original benefit of the elevated S/D engineering, is maintained by the present technique. The present self-aligned pocket procedure is very promising as a key technology beyond the 0.1 µm node.