Koichiro Ban

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

A fully-integrated single-chip CMOS transceiver with MAC and PHY for 60GHz proximity wireless communication is presented. A 60GHz wireless communication single-chip transceiver has not yet been reported due to large power consumption issues. However, by limiting the application to high-throughput proximity transmission, thermal issues arising in a single-chip have been overcome. A 2GHz broadband OFDM single-chip transceiver suffers from SNR degradation due to the reference clock (REFCLK) and baseband clock (BBCLK) spurs in RF/analog circuits. Low frequency spurs in the clock generator (CLKPLL) due to the mixing of the ADC/DAC sampling clock (SCLK) and other clocks such as REFCLK and BBCLK have been eliminated by careful frequency planning of those clocks. In addition to that, spur suppression in digital baseband and noise-tolerant RF/analog circuit designs are employed. The spurs have been successfully suppressed to less than -35dBc. The chip achieves a PHY data-rate of 2.35Gb/s and MAC throughput of 2.0Gb/s at a distance of 4cm. Power consumption is scalable to the throughput by the introduction of fast Sleep and Awake modes. The average power consumption at a throughput of 0.2Gb/s is reduced to 36% of that at 2.0Gb/s.

Digital Baseband IC Design of OFDM PHY for a 60GHz Proximity Communication System

This paper presents a digital baseband IC design based on OFDM PHY for a 60GHz proximity communication system. We propose a low computational complexity OFDM demodulator with a carrier frequency offset estimation method in polar coordinates suitable for high-speed parallel architecture. The proposed architecture is implemented in 65nm CMOS technology, and is experimentally verified to achieve the PHY data rate above 2.2Gbps. The digital baseband IC includes a complete functionality of OFDM transceiver with error correcting codecs and MAC.