Akihide Sai

A 570fs rms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop

Sampling clock jitter significantly degrades the circuit performance and dynamic range of an ADC [1]. This paper presents a 570fsrms integrated-jitter 1.21GHz PLL with a hybrid loop. A ring VCO has a much inferior phase noise characteristic as compared to an LC VCO, but its area efficiency is attractive. To suppress the phase noise of a ring VCO, a wide-loop-bandwidth PLL with sufficiently low in-band noise is indispensable. An all-digital PLL (ADPLL) [2] has insufficiently low in-band phase noise because of the quantization error of the time-to-digital converter (TDC) without employing additional techniques such as power-hungry time amplification [3]. On the other hand, a conventional analog PLL has a superior in-band phase noise but needs a large loop-filter capacitor to maintain a wide tuning range due to a high control sensitivity of the ring VCO. The dual-tuning topology is useful for minimizing the size of the loop filter while maintaining low in-band phase noise [4, 5]. However, it also suffers from strong reference spurs, as it is the case in the conventional analog PLL having a wide loop bandwidth. The proposed PLL employs a hybrid loop consisting of a type-II ADPLL and a type-I analog PLL. The type-II ADPLL enables the wide tuning range without a large loop-filter capacitor. The loop-filter capacitor in the analog PLL is also minimized since it does not need to cover a wide tuning range. The analog PLL eliminates the residual quantization error of the TDC in the ADPLL and achieves a sufficiently low in-band phase noise. Overall, the proposed PLL suppresses the phase noise contribution from the ring digital/voltage-controlled oscillator (DVCO).

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

A fully-integrated single-chip CMOS transceiver with MAC and PHY for 60GHz proximity wireless communication is presented. A 60GHz wireless communication single-chip transceiver has not yet been reported due to large power consumption issues. However, by limiting the application to high-throughput proximity transmission, thermal issues arising in a single-chip have been overcome. A 2GHz broadband OFDM single-chip transceiver suffers from SNR degradation due to the reference clock (REFCLK) and baseband clock (BBCLK) spurs in RF/analog circuits. Low frequency spurs in the clock generator (CLKPLL) due to the mixing of the ADC/DAC sampling clock (SCLK) and other clocks such as REFCLK and BBCLK have been eliminated by careful frequency planning of those clocks. In addition to that, spur suppression in digital baseband and noise-tolerant RF/analog circuit designs are employed. The spurs have been successfully suppressed to less than -35dBc. The chip achieves a PHY data-rate of 2.35Gb/s and MAC throughput of 2.0Gb/s at a distance of 4cm. Power consumption is scalable to the throughput by the introduction of fast Sleep and Awake modes. The average power consumption at a throughput of 0.2Gb/s is reduced to 36% of that at 2.0Gb/s.

A digitally stabilized type-III PLL using ring VCO with 1.01ps rms integrated jitter in 65nm CMOS

The design of low-jitter VCO-based PLLs is quite challenging as high VCO control gain, KVCO, increases the phase noise contribution arising from the charge pump and loop filter. To resolve this problem, dual-tuning PLLs (DT-PLLs) have been studied [1-4]. The DT-PLL structure adds a narrow-bandwidth coarse (high-KVCO) path to the fine (low-KVCO) path consisting of a type-II PLL. The narrow-bandwidth analog filter in the coarse path plays an important role in preventing the charge pump and the loop filter from increasing the output jitter, while a wide-tuning range is maintained. Moreover, the coarse path adds another pole at origin to the fine path and transforms it from a type-II to type-III PLL [3-4]. Compared to a type-II PLL, owing to its boosted low-frequency loop gain, a type-III PLL can better suppress a low-frequency disturbance to the ring VCO, such as temperature drift. However, a type-III PLL has stability problems. To ensure sufficient phase margin (PM), a type-III PLL requires an extremely narrow-bandwidth (e.g. ~10-100Hz) analog filter in the coarse path or must make the KVCO of the fine path larger. The former requires a nano-Farad capacitor or a fairly complex design for shrinking the capacitance, while the latter way increases total jitter. This paper presents a digitally stabilized type-Ill PLL with a ring VCO. It employs a DT-PLL structure and improves its stability by composing the coarse path with a digital integrator and a digital-to-analog converter (DAC). It can set the Kvco of the fine path to 10MHz/V, which is 1000χ lower than that of the coarse path with a sufficient PM. For further in-band phase-noise reduction, the proposed type-Ill PLL adopts a sub-sampling PLL (SS-PLL) in its fine path [5], and achieves 1.01 psrms integrated jitter.

A low-jitter clock generator based on ring oscillator with 1/f noise reduction technique for next-generation mobile wireless terminals

Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). This paper describes a low jitter clock generator for next-generation mobile wireless terminals. The clock generator employs a novel slew rate balancing (SRB) circuit in a single-ended ring oscillator based VCO to suppress the VCO phase noise due to up-converted 1/f noise. The proposed clock generator is fabricated in a 90-nm CMOS technology. The measured results show that the SRB circuit reduces the VCO phase noise by 3-5 dB at the offset frequencies where the up-converted 1/f noise dominates. The clock generator achieves 3.0 ps rms integrated jitter. Required chip area is 0.18 mm2 and the power consumption is 9 mW.

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS

Various Ultra-Low-Power (ULP) RX architectures [1-4] for Bluetooth™ Low Energy (BLE) have been developed for minimizing the RX power consumption. A PLL-based RX architecture [1] is very attractive to improve the energy efficiency. While the single-channel configuration without multi-bit ADC realizes under 3mW power consumption and over -90dBm sensitivity, the 2nd and 3rd Adjacent Channel Interference Rejections (ACRs) do not meet the BLE requirements. Although the ACR can be improved by inserting high-order LPFs into the regeneration loop, it critically degrades the closed-loop stability. The Sliding IF (SIF) architecture is an alternative approach to overcome the ACR issue with high-energy efficiency. The reported receivers in [2,3] succeed in achieving over 20dB ACR, however, the SIF still has a problem of low out-of-band blocker tolerance because of unwanted signal at the image frequency. An off/on chip bandpass filter inserted at the front of the LNA can reject the image signal, which incurs a signal loss and degrades the energy efficiency of the RX. This paper presents a new PLL-based RX with hybrid loop that achieves over 20dB 2nd/3rd ACR without any external RF filters. The proposed RX employs two key features: (1) the high-interference-tolerance hybrid-loop structure based on an ADPLL, and (2) a novel single-channel receiving method, which enables the conversion of the constellation from FSK to a differential BPSK (DBPSK) signal.

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

This paper presents a low-power hybrid-loop receiver (RX) with high-interference tolerance for Bluetooth low energy (BLE). The hybrid-loop structure based on an all-digital phase-locked loop enables the RX to both enhance the interference tolerance and digitize the frequency-modulated signal without an ADC. A novel single channel receiving method, which enables the conversion of the constellation from frequency shift keying to differential binary phase shift keying signal, is adopted to eliminate the Q-channel signal processing to reduce the power consumption. The prototype RX fabricated in a 65 nm CMOS technology consumes only 5.5 mW and fulfills the BLE requirements of the adjacent channel rejection and out-of-band blocker tolerance without exception. The sensitivity level is -90 dBm.

A low-power high-Q matching LNA with small-size matching calibration circuit for low power receiver

To reduce power consumption of the receiver, high-Q matching low noise amplifier (LNA) can be used to reduce the power consumption of the LNA. In this work, we propose a small-size high-accuracy calibration circuit for the high-Q matching LNA. The proposed circuit is constructed by two power detectors and a comparator, which has overall area of 75×35μm2 in a 65 nm CMOS process. By comparing the amplitudes of differential input signals, the optimum setting of the matching circuit is determined. The proposed method can achieve high accuracy matching calibration without the knowledge of the input power. A LNA with proposed calibration circuit is fabricated by 65 nm CMOS process. The evaluation result proves the proposed calibration method effectiveness.

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique

Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and high-resolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1–3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1–2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements.

19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC

Several research studies have considered replacing traditional analog PLLs with an all-digital PLL (ADPLL). In such studies, a key topic relates to the resolution and linearity of the TDC. Power-hungry techniques, such as a Vernier delay line (VDL) and a time amplifier (TA) [1,2], have been proposed to improve time resolution. Recently, a digital-to-time converter (DTC) has been employed to enable power reductions of the VDL and TA-based TDCs by minimizing the number of VDLs and TAs [3,4]. However, the nonlinearity of the DTC remains a problem, since it is much larger than the time resolution of the TDCs and becomes a significant source of fractional spur in the ADPLL. In [3], the effect of the nonlinearity is decreased by utilizing a dithering technique at the expense of a long calibration time (> 100ms). The DTC requires inherently more calibration effort for full-scale-delay detection and normalization, since the difference between the full-scale delay and the DCO period also increases the fractional spur significantly. On the other hand, time-to-amplitude-conversion-based TDCs may be another candidate for a high-resolution low-power TDC [5]. However, issues surrounding the nonlinearity of the charge pump (CP) and the full-scale-delay detection limit their utility.

A wide bandwidth analog front-end circuit for 60-GHz wireless communication receiver

This paper presents an analog front-end circuit for a 60-GHz wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224 mW Power consumption.