Hiroaki Hoshino

A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications

The fisrt 77 GHz frequency modulated continuos wave (FMCW) radar transceiver IC with an accurate FMCW signal generator using a 90 nm CMOS process is presented. To realize accurate FMCW radar system in CMOS, a PLL synthesizer that is able to output linear FMCW frequency is applied. Measured radar performances, output spectrum and distance of a target, show the transceiver achieves a fundamental function for radar applications.

A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS

A 60-GHz phase-locked loop (PLL) with inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80 x 40 mum2. The active area of the PLL is 0.6 x 0.6 mm2.

A 60-GHz CMOS Receiver with Frequency Synthesizer

A 60-GHz receiver (RX) chip fabricated in 90 nm CMOS process is reported. The RX chip consists of an LNA, a downconversion mixer and a phase-locked loop synthesizer. The RX chip is capable of generating LO signal from phase-locked synthesizer. Measured power gain and NF of 22 dB and 8.4 dB were obtained at 61.5 GHz. These results indicate the possibility of realization of CMOS single-chip 60-GHz transceiver.

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

A fully-integrated single-chip CMOS transceiver with MAC and PHY for 60GHz proximity wireless communication is presented. A 60GHz wireless communication single-chip transceiver has not yet been reported due to large power consumption issues. However, by limiting the application to high-throughput proximity transmission, thermal issues arising in a single-chip have been overcome. A 2GHz broadband OFDM single-chip transceiver suffers from SNR degradation due to the reference clock (REFCLK) and baseband clock (BBCLK) spurs in RF/analog circuits. Low frequency spurs in the clock generator (CLKPLL) due to the mixing of the ADC/DAC sampling clock (SCLK) and other clocks such as REFCLK and BBCLK have been eliminated by careful frequency planning of those clocks. In addition to that, spur suppression in digital baseband and noise-tolerant RF/analog circuit designs are employed. The spurs have been successfully suppressed to less than -35dBc. The chip achieves a PHY data-rate of 2.35Gb/s and MAC throughput of 2.0Gb/s at a distance of 4cm. Power consumption is scalable to the throughput by the introduction of fast Sleep and Awake modes. The average power consumption at a throughput of 0.2Gb/s is reduced to 36% of that at 2.0Gb/s.

A 60-GHz CMOS power amplifier with Marchand balun-based parallel power combiner

A novel Marchand balun-based parallel power combiner suitable for a 60-GHz CMOS power amplifier is proposed. It improves the power efficiency by solving the issues of the phase difference of the signals to be combined and the low coupling factor of the on-chip balun in scaled CMOS technologies. The power amplifier using the proposed power combiner is fabricated in a 90 nm CMOS process with 1.2 V supply. Measured power gain, output referred 1-dB compression point, and saturated output power are 11.2 dB, +8.3 dBm, and +11.2 dBm, respectively, at 60-GHz.

High-Q MOS-varactor modeling for mm-wave VCOs

High-Q and scalable MOS varactor for mm-wave VCO has been studied. To realize high-Q varactor in mm-wave region, low varactor capacitance and low series resistance of unit cell are essential. Since low varactor capacitance and low series resistance are impossible to realize simultaneously, optimization and scalable model are necessary. This paper presents strategy of high-Q optimization, a novel scalable model for mm-wave varactor, and confirmation results by VCO measurements. The Q of small-geometry varactor improved 30 times at f =30 GHz. The novel scalable varactor model improved its accuracy from 21.9% to 1.7%.

A 0.13/spl mu/m CMOS 5GHz Fully Integrated 2x3 MIMO Transceiver IC with over 40dB Isolation

A 5 GHz MIMO direct-conversion transceiver composed of 2 transmitters (TXs) and 3 receivers (RXs) is fabricated with 0.13 mum CMOS technology. Die size is 4.56 mm times 7.7 mm. For driving 10 GHz LO signal lines of 5 mm length for both TXs and RXs, inductor-less low-power LO repeaters are equipped in individual LO paths. A linearized RF variable gain amplifier is proposed for low power operation. Isolation of over 40 dB is obtained by equipping separate GNDs on both the MIMO IC and the circuit board. This results in negligible degradation of EVM. TX EVM of over -31 dB is obtained at -8.6 dBm for 2 TX mode when external LO of 10 GHz is applied. The 3 RXs and 2 TXs with LO paths dissipate 703 mW and 412 mW from 1.5 V, respectively.