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Dive into the research topics where Koji Ichimura is active.

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Featured researches published by Koji Ichimura.


Journal of Micro-nanolithography Mems and Moems | 2016

Development of nanoimprint lithography templates toward high-volume manufacturing

Koji Ichimura; Kouji Yoshida; Saburo Harada; Takaharu Nagai; Masaaki Kurihara; Naoya Hayashi

Abstract. Development of nanoimprint lithography (NIL) templates is discussed. The template fabrication process and its performance are presented with consideration of the requirements of NIL for high-volume manufacturing. Defectivity, image placement, and critical dimension uniformity are the three major performance parameters of the templates, and their current status is shown.


Proceedings of SPIE | 2015

HVM readiness of nanoimprint lithography templates: defects, CD, and overlay

Koji Ichimura; Kouji Yoshida; Saburo Harada; Takaharu Nagai; Masaaki Kurihara; Naoya Hayashi

Performances of the nanoimprint lithography templates were discussed considering the readiness toward the high volume manufacturing of nanoimprint lithography application along with the requirement for the templates and its fabrication process. The current status of the three major performances of the templates was shown.


SID Symposium Digest of Technical Papers | 2008

23.3: Flexible Field‐Sequential‐Color FLCD Panels Driven by poly‐Si TFTs

Yoji Iwamoto; Katsuyuki Motai; Yasunori Naitou; Masaru Kadowaki; Koji Ichimura; Hiroto Sato; Yoshihide Fujisaki; Toshihiro Yamamoto; Hideo Fujikake; Taiichiro Kurita

A novel flexible field-sequential-color FLCD panel driven by poly-Si TFTs has been developed. A 16×16 active matrix panel was fabricated using polymer stabilized FLC and poly-Si TFTs fabricated onto plastic substrate below 150°C, and colored moving images were demonstrated on the panel with frame frequency of 60Hz.


Japanese Journal of Applied Physics | 2008

Improvement in SiO2 Film Properties Formed by Sputtering Method at 150 °C

Yuji Urabe; Toshiyuki Sameshima; Katsuyuki Motai; Koji Ichimura

The quantity of hysteresis phenomena in capacitance response for metal–oxide–semiconductor (MOS) capacitors with 100-nm-thick SiO2 films formed by the sputtering method was reduced by remote oxygen plasma treatment followed by high-pressure H2O vapor heat treatment at 150 °C. In order to determine the quantity of hysteresis phenomena in capacitance response, we defined hysteresis charge as the difference in fixed oxide charge density for round bias voltage application. As-fabricated MOS capacitor samples had a high density of hysteresis charges of 1.0×1012 cm-2. The density of hysteresis charge was not decreased by 4.7×105-Pa-H2O-vapor heat treatment at 150 °C for 3 h. On the other hand, it was markedly reduced to 1.0×1011 cm-2 by 13.56-MHz-radio frequency remote oxygen plasma treatment at 300 W and 150 °C followed by 4.7×105-Pa-H2O-vapor heat treatment at 150 °C for 3 h. Hysteresis phenomena are probably caused by a temporal electron charging up of SiO2 films.


Japanese Journal of Applied Physics | 2010

Defect Reduction in Polycrystalline Silicon Thin Films at 150 °C

Toshiyuki Sameshima; Yuta Mizutani; Katsuyuki Motai; Koji Ichimura

We report defect reduction in 50-nm-thick laser-crystallized polycrystalline silicon (poly-Si) films by a combination of hydrogen plasma at 100 W for 5 s at room temperature with 4.7×105 Pa H2O vapor heat treatment at 150 °C for 6 h. The present treatment increased the photoconductivity to 1×10-3 S/cm for undoped poly-Si films under the illumination of 532 nm light at 100 mW/cm2. It also increased the electrical conductivity to 30 S/cm for 2×1019 cm-3 phosphorus-doped poly-Si films. Those values were comparable to those for samples treated with 1.3×106 Pa H2O vapor heat treatment for 3 h at 260 °C. Hydrogen concentration increased from 1.6 to 5.4 at. % as hydrogen plasma duration increased from 5 to 120 s. It was decreased by subsequent H2O vapor heat treatment at 150 °C, and ultimately ranged from 1.1 to 4.5 at. %. Hydrogen atoms play a catalytic role in the dissociation of H2O molecules at 150 °C.


Photomask Technology 2018 | 2018

Sub-15nm template fabrication with multi-beam mask writer (Conference Presentation)

Koji Ichimura; Koichi Kanno; Masaaki Kurihara; Naoya Hayashi

Nanoimprint lithography, NIL, is an attractive low cost lithography technique especially for a non-volatile memory device application. The advantages of NIL are simpler exposure system with no coat/dev track, single process step without SADP/SAQP, less design rule restriction, lower cost-of-ownership, compared with other lithography technologies. NIL working templates are made by the replication of the EB written high quality master templates. Fabrication of high resolution master templates is one of the key items, so as to realize high quality replica templates by carefully controlled replication process. Application of multi-beam mask writer, MBMW, to the NIL master template fabrication is very attractive for the coming generation of the new memory devices. For a fine feature master template such as 1z nm node, shot counts for writing with single beam tool will increase drastically and the writing time is estimated more than days. On the other hand, because of the parallel exposure principle, MBMW can write a master in a certain time for any feature size. In addition, MBMW is suitable for high resolution low sensitivity EB resist, which is evitable for fine feature master fabrication of lines and holes. We applied MBMW for the fabrication sub-15nm feature size templates. A full-field 1x master template was fabricated. In this presentation, we will be discussing master template fabrication process with MBMW and the performance of the template. We will also discuss the replication process with a high resolution master.


Emerging Patterning Technologies 2018 | 2018

Fabrication of full-field 1z nm template using multi-beam mask writer (Conference Presentation)

Koji Ichimura; Koichi Kanno; Masaaki Kurihara; Naoya Hayashi

Nanoimprint lithography, NIL, is gathering much attention as one of the most promising candidates for the next generation lithography for semiconductor. The advantages of NIL are simpler exposure system with no coat/dev track, single process step without SADP/SAQP, less design rule restriction, lower cost-of-ownership, compared with other lithography technologies. NIL working templates are made by the replication of the EB written high quality master templates. Fabrication of high resolution master templates is one of the key items. Since NIL is 1:1 pattern transfer process, master templates have to have 4 times higher resolution compared with conventional photomasks. Another key is to maintain the quality of the master templates in replication process. NIL process is applied for the template replication and this imprint process determines most of the performance of the replicated templates. Application of multi-beam mask writer, MBMW, to the NIL master template fabrication is very attractive. For a fine feature master template such as 1z nm node, shot count for writing with single beam tool will drastically increase and the writing time is estimated more than days. On the other hand, because of the parallel exposure principle, MBMW can write a master in a certain time for any feature size. In addition, MBMW is suitable for high resolution low sensitivity EB resist, which is evitable for fine feature master fabrication. We applied MBMW for the fabrication of full-field master of 1z nm node. In this presentation, we will be discussing master template fabrication process with MBMW and the performance of the template. We will also discuss the replication process with a high resolution master.


Proceedings of SPIE | 2017

Development of nanoimprint lithography templates for the contact hole layer application (Conference Presentation)

Koji Ichimura; Ryugo Hikichi; Saburo Harada; Koichi Kanno; Masaaki Kurihara; Naoya Hayashi

Nanoimprint lithography, NIL, is gathering much attention as one of the most potential candidates for the next generation lithography for semiconductor. This technology needs no pattern data modification for exposure, simpler exposure system, and single step patterning process without any coat/develop truck, and has potential of cost effective patterning rather than very complex optical lithography and/or EUV lithography. NIL working templates are made by the replication of the EB written high quality master templates. Fabrication of high resolution master templates is one of the most important issues. Since NIL is 1:1 pattern transfer process, master templates have 4 times higher resolution compared with photomasks. Another key is to maintain the quality of the master templates in replication process. NIL process is applied for the template replication and this imprint process determines most of the performance of the replicated templates. Expectations to the NIL are not only high resolution line and spaces but also the contact hole layer application. Conventional ArF-i lithography has a certain limit in size and pitch for contact hole fabrication. On the other hand, NIL has good pattern fidelity for contact hole fabrication at smaller sizes and pitches compared with conventional optical lithography. Regarding the tone of the templates for contact hole, there are the possibilities of both tone, the hole template and the pillar template, depending on the processes of the wafer side. We have succeeded to fabricate both types of templates at 2xnm in size. In this presentation, we will be discussing fabrication or our replica template for the contact hole layer application. Both tone of the template fabrication will be presented as well as the performance of the replica templates. We will also discuss the resolution improvement of the hole master templates by using various e-beam exposure technologies.


Archive | 1998

Reflection-type liquid crystal display panel and method of fabricating the same

Koji Ichimura


Archive | 2010

Substrate for flexible device, thin film transistor substrate for flexible device, flexible device, substrate for thin film element, thin film element, thin film transistor, method for manufacturing substrate for thin film element, method for manufacturing thin film element, and method for manufacturing thin film transistor

Shunji Fukuda; Katsuya Sakayori; Keita Arihara; Koji Ichimura; Kei Amagai

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