Koji Shibutani

An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology

We propose an on-die aging monitor based on ring-oscillator (RO) which measures bias-temperature-instabilities (BTI) and AC hot-carrier-infection (HCI). The monitor consists of a symmetric RO (SRO) and an asymmetric RO (ASRO). The effect of NBTI and PBTI can be separated by focusing on the difference in sensitivity observed in SRO and ASRO under DC stress condition. In addition, the speed degradation caused by AC-HCI is monitored because unbalanced delay with long/short transition in ASRO has high sensitivity against AC-HCI under AC stress. A test chip including both SRO and ASRO using 2NAND standard cells is implemented in a 16 nm Fin-FET bulk CMOS technology. We observe that Vth shift due to PBTI measured from frequency degradation is 2 mV, which is still 1/10 of NBTI in Fin-FET technology. The measured AC-HCI shows almost half percentage of all aging factors. The aging monitor optimizes the design guard band (GB) in design phase and enables dependable system in high performance application LSIs.

A novel high accurate analytical technique of the leak current for the product chip

We propose the novel technique to analyze the leak current of the product chip accurately. Comparison of calculated and measured leak current proves the validity of this technique. The small variation causation of the products leak current is able to be analyzed. Moreover, leak current reduction guide is obtained with the detail component factor analysis. Applying to the in-line monitor, all wafers could be an analytical object.

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology

We have developed a power-gating technique for a mobile processor in 28-nm HKMG technology. The proposed EM-tolerant 1.8V I/O NMOS power switch reduces the standby power to 1/641× and achieves 79% channel utilization without weakening EM immunity. The active leakage power of the dual CPU cores can be reduced by 45 mW in a single core operation mode with a rapid 1.4-μs wakeup time to full core operation. A mobile processor is designed and fabricated with proposed technique. Estimated standby power of the chip is 123 μW, resulting in one order of magnitude reduction compared to the conventional techniques. Measured leakage power shows a good agreement with the estimated one.

Wear-out stress monitor utilising temperature and voltage sensitive ring oscillators

The authors propose an on-chip wear-out monitoring technique, which is based on monitoring the environmental conditions experienced by a digital circuit. The frequency of the T-sensitive ring oscillator (RO) emulates the wear-out stress strength caused by the temperature conditions based on the model of exponential dependence of the stress on the inverse of temperatures. The frequency of the VT-sensitive RO emulates the stress due to time-dependent dielectric breakdown, which is stressed by voltages as well as temperatures. Thus, the accumulated counts driven by the ROs directly indicate the total wear-out stress that the product has experienced so far. The measured results of a test chip fabricated by 28 nm High-k Metal Gate process confirm the expected dependence of T-/VT-sensitive RO frequencies on temperatures and voltages, enabling the emulation of wear-out. The methodology is presented to estimate the stress amount of various wear-out factors having different thermal activation energies. The proposed wear-out stress monitor would make automotive microcontrollers more reliable when they operate at boosted voltages and elevated temperatures to meet performance requirements of cutting-edge applications such as advanced driver assistance systems.

FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs

We propose wear-out estimator of remaining lifetime, which consists of two types of custom ring oscillators (ROs) and cumulative stress counters only. This on-chip estimator operates independently without disruption of MCU main operations and is aimed for advanced automotive MCUs, which demand sufficient reliability and real-time response along with high performance in cutting-edge applications such as ADAS. One of the custom ROs is temperature sensitive RO, which achieves the count-up speed proportional to exp(-Ea/kT), thus enabling estimation of the accumulated electro-migration (EM) stress that the die has experienced thus far. The other RO is voltage and temperature sensitive RO, which achieves the count-up speed proportional to Vn*exp(-Ea/kT) for use in TDDB stress estimation. The test chip of the custom ROs was fabricated by using 28nm HKMG process. The measured result successfully emulates more than one order of magnitude difference between 125C and 85C EM stress and 10× combinational accentuation of TDDB stress under simultaneous high voltage and temperature.

Area and performance study of FinFET with detailed parasitic capacitance analysis in 16nm process node

An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a delay cell because it is easy to increase delay time with simple layout modification only. Moreover, small number of delay cell can reduce a leakage current in a chip.

Assessment of reliability impact on GHz processors with moderate overdrive

Moderate overdrive of the supply voltage rather reduces total powers at high temperatures, which enables GHz design overcoming thermal runaway. We have examined the way in which reliability issues such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) affect the product performance. 1) The high temperature and voltage acceleration test on 45nm products has revealed that NBTI variations have small impacts on the amount of the voltage guard-band which is set at the product testing to prevent the wear-out failures in advance. 2) The increase in the voltage guard-band by using moderate overdrive is small enough compared to the amount of moderate overdrive voltage. 3) The HCI AC-to-DC ratio is expected to increase as the process scaling proceeds, making the HCI less influential. These aspects enable low-power and reliable GHz design utilizing moderate overdrive.

A novel compact model of the product marginal yield and its application for performance maximization

In this paper, we present a novel compact model to calculate the product performance accurately. The compact model is constructed by leakage current and active speed calculation of logic circuit. It becomes possible to estimate marginal yield before pilot wafer by the input of a little Si information (Ring Oscillator frequency, leakage of transistor, wiring capacitance, transistor variability) to the compact model. It is effective to change a transistor target in order to improve marginal yield and maximize product performance. In the case of increasing the CPU frequency by 25% using the same process technology, we can improve marginal yield about 15% by using this method before pilot wafer.