Takeshi Okagaki

Application of a statistical compact model for Random Telegraph Noise to scaled-SRAM Vmin analysis

A statistical compact RTN (Random Telegraph Noise) model with a fixed V<inf>th</inf> shift and V<inf>gs</inf> dependent trap time constants is proposed. It accurately reproduces the experimental observation of larger V<inf>th</inf> fluctuation at higher |V<inf>gs</inf>|. The model is also applied to analysis of SRAM V<inf>min</inf> fluctuation and finds out the distribution follows a log-normal statistics.

Direct measurement of stress dependent inversion layer mobility using a novel test structure

We propose a novel mobility measurement method which can be applied to industrial sized MOSFETs. The mobility variation caused by Shallow Trench Isolation (STI) stress is evaluated directly. Extracted piezoresistance coefficients in the inversion layer are close to their counterparts in bulk silicon. The stress effect model like that incorporated into BSIM4.3.0 is verified to adequately predict the behavior. Additionally, we have observed for the first time that the inversion layer mobility in <100> channel MOSFETs is less sensitive to the STI stress than that in <110> channel along MOSFETs. Therefore, CMOS devices with layouts the <100> direction is expected to have high performance with reduced source of design complication.

Impact of Shear Strain and Quantum Confinement on 110 Channel nMOSFET With High-Stress CESL

Numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along in terms of the device performance of strained 65nm-node nMOSFETs with Contact Etch Stop Layer (CESL), and that both the shear strain component and the quantum confinement effect play an important role in this superiority.

An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology

We propose an on-die aging monitor based on ring-oscillator (RO) which measures bias-temperature-instabilities (BTI) and AC hot-carrier-infection (HCI). The monitor consists of a symmetric RO (SRO) and an asymmetric RO (ASRO). The effect of NBTI and PBTI can be separated by focusing on the difference in sensitivity observed in SRO and ASRO under DC stress condition. In addition, the speed degradation caused by AC-HCI is monitored because unbalanced delay with long/short transition in ASRO has high sensitivity against AC-HCI under AC stress. A test chip including both SRO and ASRO using 2NAND standard cells is implemented in a 16 nm Fin-FET bulk CMOS technology. We observe that Vth shift due to PBTI measured from frequency degradation is 2 mV, which is still 1/10 of NBTI in Fin-FET technology. The measured AC-HCI shows almost half percentage of all aging factors. The aging monitor optimizes the design guard band (GB) in design phase and enables dependable system in high performance application LSIs.

Stress from Discontinuous SiN Liner for Fully Silicided Gate Process

New materials often force modification in a metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process and a device structure. In our investigation, a high-stress silicon nitride (SiN) contact etch stopper layer (CESL), which improves device performance by straining the Si lattice, was used as the modified structure. A portion of its gate surround was cut to fabricate a fully silicided (FUSI) metal gate. FET characteristics of a polycrystalline silicon (poly-Si) gate and a Ni-FUSI gate MOSFET with a discontinuous CESL were compared with those of a poly-Si gate MOSFET with an ordinary continuous CESL for several SiN-stress conditions. It was found that the removal of a gate-top CESL diminishes mobility modulation effects of a high-stress CESL. It was also demonstrated that stress due to a FUSI gate compensates the effect of gate-top CESL removal. Mobility enhancement utilizing a high-stress SiN film was still effective for a FUSI gate process.

Impact of Shear Strain and Quantum Confinement on

In this paper, we propose a new analytical electron mobility model in strained Si inversion layers suitable for implementation in a drift-diffusion simulator. Using our new model, a numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along <110> in terms of the device performance of strained 65-nm-node nMOSFETs with contact etch stop layer and that both the shear-strain component and the quantum confinement effect are key factors in contributing to this superiority.

\langle\hbox{110}\rangle

A novel methodology is presented to generate the worst-case model including extraction of its compact model parameters. This method enables physically accurate worst-case prediction in the early stage of device development concurrently. It is found through the intensive TEG analysis and TCAD simulation that correlations between process factors have a significant impact on the worst-case corner estimation. A new extraction method of compact model parameters based on error propagation analysis is developed to consider correlations between parameters

Channel nMOSFET With High-Stress CESL

We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.

Global Identification of Variability Factors and Its Application to the Statistical Worst-Case Model Generation

Test structures for measuring characteristics of MOS components in 28 nm high-k metal-gate (HKMG) Ternary Content-Addressable memory (TCAM) bitcell are implemented. Proposed TCAM bitcell are including pull-down (PD) and pass-gate (PG) NMOSs, pull-up (PU) PMOSs and search NMOSs, which are built up based on standard 6T SRAM bitcell. It can achieve the small area but symmetrical layout could not be implemented. Each MOS characteristic is measured by test structure and observed over 20 mV Vt offset for each PD and PG NMOS pairs due to asymmetrical layout, whereas there is no difference in PU-PMOS pair. From measurement results we estimate the bit error rates on the supply voltage for TCAM array and predict that the TCAM Vmin for read-operation becomes worse by 42 mV at 5.3-sigma condition compared to that of standard SRAM array. Based on measured bitcell characteristics we designed and fabricated 80-Mbit TCAM test chips with appropriate redundancies, achieving below 740 mV Vmin at 250 MHz operation at 25°C and 85°C.

2RW dual-port SRAM design challenges in advanced technology nodes

We propose the novel technique to analyze the leak current of the product chip accurately. Comparison of calculated and measured leak current proves the validity of this technique. The small variation causation of the products leak current is able to be analyzed. Moreover, leak current reduction guide is obtained with the detail component factor analysis. Applying to the in-line monitor, all wafers could be an analytical object.