Mitsuhiko Igarashi

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are as follows. 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2 GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28 nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), resulting in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40 mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC voltage drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.

Direct measurement of stress dependent inversion layer mobility using a novel test structure

We propose a novel mobility measurement method which can be applied to industrial sized MOSFETs. The mobility variation caused by Shallow Trench Isolation (STI) stress is evaluated directly. Extracted piezoresistance coefficients in the inversion layer are close to their counterparts in bulk silicon. The stress effect model like that incorporated into BSIM4.3.0 is verified to adequately predict the behavior. Additionally, we have observed for the first time that the inversion layer mobility in <100> channel MOSFETs is less sensitive to the STI stress than that in <110> channel along MOSFETs. Therefore, CMOS devices with layouts the <100> direction is expected to have high performance with reduced source of design complication.

An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology

We propose an on-die aging monitor based on ring-oscillator (RO) which measures bias-temperature-instabilities (BTI) and AC hot-carrier-infection (HCI). The monitor consists of a symmetric RO (SRO) and an asymmetric RO (ASRO). The effect of NBTI and PBTI can be separated by focusing on the difference in sensitivity observed in SRO and ASRO under DC stress condition. In addition, the speed degradation caused by AC-HCI is monitored because unbalanced delay with long/short transition in ASRO has high sensitivity against AC-HCI under AC stress. A test chip including both SRO and ASRO using 2NAND standard cells is implemented in a 16 nm Fin-FET bulk CMOS technology. We observe that Vth shift due to PBTI measured from frequency degradation is 2 mV, which is still 1/10 of NBTI in Fin-FET technology. The measured AC-HCI shows almost half percentage of all aging factors. The aging monitor optimizes the design guard band (GB) in design phase and enables dependable system in high performance application LSIs.

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores

The worldwide demand for high-performance mobile or car infotainment application processors (AP) is increasing. This demand coexists with the need for low power to achieve long battery life and avoid thermal runaway. A heterogeneous CPU configuration is an effective solution. The proposed heterogeneous quad/octa-core AP has a combination of high-performance 2GHz cores and energy-efficient 1GHz cores. The maximum performance in the octa-core configuration is 35600 DMIPS. The key design highlights are: 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg). 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC IR drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.

A dynamic/static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs

An embedded SRAM power management scheme using 16 nm FinFET technology is demonstrated in automotive infotainment SoCs. By introducing write-assist circuit technique, SRAM can operate down to 0.5 V wide voltage range, achieving DVFS for efficient power saving. Fast resume standby mode is also developed for reducing the leakage power of L1 cache under 2 GHz CPU operation. We confirmed that proposed thermal control scheme can be protected by thermal runaway failure.

Assessment of reliability impact on GHz processors with moderate overdrive

Moderate overdrive of the supply voltage rather reduces total powers at high temperatures, which enables GHz design overcoming thermal runaway. We have examined the way in which reliability issues such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) affect the product performance. 1) The high temperature and voltage acceleration test on 45nm products has revealed that NBTI variations have small impacts on the amount of the voltage guard-band which is set at the product testing to prevent the wear-out failures in advance. 2) The increase in the voltage guard-band by using moderate overdrive is small enough compared to the amount of moderate overdrive voltage. 3) The HCI AC-to-DC ratio is expected to increase as the process scaling proceeds, making the HCI less influential. These aspects enable low-power and reliable GHz design utilizing moderate overdrive.

28-nm HKMG GHz digital sensor for detecting dynamic voltage drops in testing for peak power optimization

We propose a dynamic voltage-drop sensor, which is fully digital so that it is easy to design into products and use for testing. The 2.4K-gate GHz sensor exploits the difference in the voltage sensitivity between two paths composed of different types of standard cells. We have fabricated a test chip in a 28-nm HKMG process and confirmed its feasibility. This sensor can be used to evaluate optimal activity rates and peak power in scan testing.