Kong-Soo Lee

Cost-Effective Silicon Vertical Diode Switch for Next-Generation Memory Devices

In this letter, a cost-effective vertical diode scheme for next-generation memory devices, including phase-change memories (PCMs), is realized. After the contact formation for diodes with only one mask layer, an amorphous silicon (a-Si) film was deposited within the contacts using SiH4 ramp-up ambient in a conventional batch-type furnace in order to minimize the growth of native oxide. A deposition/etch-back/deposition scheme enabled us to achieve robust vertical diodes without any seams or interfacial oxide layer within the vertical diode pillars. Subsequent annealing at 600 °C provided solid-phase epitaxial alignment of the a-Si layer. An ideality factor revealed that the new scheme provided noticeable crystallinity of the silicon diodes. Moreover, the electrical characteristics of the diodes verified that the scheme was suitable for full operation of PCM devices.

Low-Temperature Solid Phase Epitaxial Regrowth of Silicon for Stacked Static Random Memory Application

Solid phase epitaxy (SPE) techniques have been studied to realize stacked static random memory (SRAM) devices. Among the candidates including epitaxial lateral overgrowth (ELO) and laser epitaxial growth (LEG) techniques, SPE is the most stable and cost-effective scheme since it is fulfilled by the deposition of amorphous silicon layers and the subsequent low temperature annealing using conventional furnace equipment which has been used for several decades in semiconductor fabrication. We introduced silicon seeds for the epitaxial realignment of amorphous silicon within the contact window by the selective epitaxial growth (SEG) of single-crystalline silicon. The role of process variables associated with channel silicon deposition on SPE was investigated. The efficiency of SPE was quantified by electron back-scatter diffraction (EBSD) measurement, which visualizes the fraction of the orientation in a channel silicon layer. SiH4 ambient during the ramp-up stage in the deposition of amorphous silicon layers showed superior epitaxial realignment to N2 ambient, which was mainly due to the suppression of interfacial layer formation. Electrical characteristics such as on-current distribution and static noise margin indicated SPE to be feasible for high-density stacked SRAM application.

Ge Implantation to Improve Crystallinity and Productivity for Solid Phase Epitaxy Prepared by Atomic Mass Unit Cross Contamination-Free Technique

Germanium (Ge) ion implantation was investigated for crystallinity enhancement during solid phase epitaxial (SPE) regrowth. Electron back-scatter diffraction (EBSD) measurement showed numerical increase of 19% of (100) signal, which might be due to the effect of pre-amorphization implantation (PAI) on silicon layer. On the other hand, electrical property such as off-leakage current of n-channel metal oxide semiconductor (NMOS) transistor degraded in specific regions of wafers. It was confirmed that arsenic (As) atoms were incorporated into channel area during Ge ion implantation. Since the equipment for Ge PAI was using several source gases such as BF3 and AsH3, atomic mass unit (AMU) contamination during PAI of Ge with AMU 74 caused the incorporation of As with AMU 75 which resided in arc-chamber and other parts of the equipment. It was effective to use Ge isotope of AMU 72 to suppress AMU contamination. It was effective to use enriched Ge source gas with AMU 72 in order to improve productivity.

Current-voltage characteristics of vertical diodes for next generation memories

In this paper, current-voltage-temperature (I-V-T) characteristics of vertical diodes realized by different selective epitaxial growth techniques have been investigated. Diodes by the batch-type cyclic SEG process at low temperature have shown eligible performances for vertical switches, including ideality factor of 1.08, off-current of 1.0×10-12 A and on/off-ratio of 2.4×108. The optimization of crystallographic defects and series resistance is expected to be the most critical for the performances of vertical diodes for next generation memories.

Electrical Extractions of One Dimensional Doping Profile and Effective Mobility for Metal--Oxide--Semiconductor Field-Effect Transistors

In this study, an attempt is made to provide a framework to assess and improve metal–oxide–semiconductor field-effect transistor (MOSFET) reliability from the early stage of the design to the completion of the product. A small gate area has very small capacitances that are difficult to measure, making capacitance–voltage (C–V) based techniques difficult or impossible. In view of these experimental difficulties, we tried electrical doping profiling measurement for MOSFET with short gate length, ultra thin oxide thickness and asymmetric source/drain structure and checked the agreement with simulation result. We could get the effective mobility by simple drain current versus drain bias voltage measurement. The calculated effective mobility was smaller than expected value and we explained some reasons. An accurate effective mobility for asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique, with the capacitance measured between the gate and source–drain and between the gate and the substrate.

Stacked FRAM capacitor etching process for high density application

Abstract In this paper, one step ferroelectric capacitor etching technology has been developed. Stacked capacitor layers with 0.75μm height were etched with a TiN hard mask. Etch selectivity increases as oxygen ratio in capacitor etching gases increases. After etching the electrodes and the PZT film, the slope of the stack capacitor was around 72 degrees and it has been proven that no si dew all fence was generated during the capacitor etching process and its leakage current was below 10–6A/cm2. The 0.9×0.9μm2 area capacitor for a 16M FRAM density has been well fabricated by one step etching process with very high selectivity to the mask.

Effects of ILD & IMD characteristics on ferroelectric properties of fram devices

Abstract We have deposited SiO2 using plasma-enhanced TEOS-based (PE-TEOS) CVD method and USG and PSG using atmosphere-pressure CVD method on Pb(Zr, Ti)O3(PZT) capacitors. The ferroelectric and dielectric properties of the SiO2 covered PZT capacitors were characterized. SIMS (secondary ion mass spectroscopy) was utilized to obtain hydrogen concentration in the deposited ILD and IMD materials. The concentration of hydrogen in the PE-TEOS-derived SiO2 was lower than that in the PSG and the USG. Internal stress was low tensile at room temperature and the behavior of thermal stress hysteresis was nearly similar for all SiO2 materials. Remnant polarization (Pr) of the PE-TEOS covered PZT capacitors was severely degraded as compared to that of as-deposited capacitors. From these results, we have concluded that the degradation of ferroelectric characteristics of PZT capacitors associated with the ILD and IMD processes was closely related to the plasma-induced damage.

Abnormal gate oxide thickening at active edge with SiN-linered shallow trench isolation

Abnormal gate oxide thickening at active edge (GOTAE) has been investigated in dynamic random access memories (DRAMs) with SiN-lineared shallow trench isolation (STI). 1% of gaseous HCl, which is added during dry oxidation, plays a major role in inducing abnormal GOTAE by the mechanical interaction with thin SiN layers in STI. Other structural parameters, such as the thickness of trench sidewall oxide, liner SiN and sacrificial oxide, are believed to influence the amount of oxide thickening. In order to avoid abnormal GOTAE, wet oxidation is introduced and shown to be effective in suppressing it. Electrical properties, which are susceptible to the extent of GOTAE, are also presented in this paper.