Sang-jin Park

Pd-nanocrystal-based nonvolatile memory structures with asymmetric SiO2∕HfO2 tunnel barrier

Pd nanocrystals (NCs) on asymmetric tunnel barrier (ATB) composed of stacked SiO2 and HfO2 layers have been employed for nonvolatile memory devices. The Pd-NC layers are formed by electrostatic self-assembly of negatively charged colloidal Pd NCs. The presence of isolated Pd NCs of ∼5nm embedded in HfO2 is confirmed by scanning and transmission electron microscopy images. Outstanding program∕erase (P∕E) properties from C‐V curves are observed with a memory window of 6V under ±17V. Extrapolation of the data up to ten years shows that the flatband voltage drops at the P∕E levels are maintained within only 1.0∕0.5V, respectively, resulting from the efficient data retention based on the ATB. These results are promising enough for the memory structure to be utilized for the multilevel charge storage.

Atomic-layer deposited IrO2 nanodots for charge-trap flash-memory devices

Charge-trap flash- (CTF) memory structures have been fabricated by employing IrO2 nanodots (NDs) grown by atomic-layer deposition. A band of isolated IrO2NDs of about 3 nm lying almost parallel to Si/SiO2 interface is confirmed by transmission electron microscopy and x-ray photoelectron spectroscopy. The memory device with IrO2NDs shows much larger capacitance–voltage (C–V) hysteresis and memory window compared with the control sample without IrO2NDs. After annealing at 800 °C for 20 min, the ND device shows almost no change in the width of C–V hysteresis and the ND distribution. These results indicate that the IrO2NDs embedded in SiO2 can be utilized as thermally stable, discrete charge traps, promising for metal oxide-ND-based CTF memory devices.

High trap density and long retention time from self-assembled amorphous Si nanocluster floating gate nonvolatile memory

The memory performance of floating gate nonvolatile memory based on amorphous Si (a-Si) nanoclusters self-assembled during low-temperature oxidation is investigated. A 2nm thick a-Si layer was grown on a top of a 5.6nm thick thermal oxide tunneling layer by ultrahigh vacuum ion beam sputter deposition and subsequently oxidized by annealing in flowing N2∕O2 (9:1) environment for 0–540s at 900°C. After oxidation, a 14nm thick Al2O3 control oxide layer was grown by atomic layer deposition. The authors find that the a-Si layer breaks up upon oxidation, self-assembling into a dense array of 1000s at at 150°C.

Anomalous light-induced enhancement of photoluminescence from Si nanocrystals fabricated by thermal oxidation of amorphous Si

A band of ∼1.6nm diameter Si nanocrystals (NCs) has been prepared at a depth of about 5nm within SiO2 by atomic-layer deposition of 2nm amorphous Si on 5nm SiO2 and subsequent thermal oxidation at 900°C. After 4h light exposure of 5.66W∕cm2, photoluminescence (PL) spectrum of the Si NCs is almost 60 times enhanced with its peak blueshifted by about 30nm. The enhancement rate of the PL intensity with illumination time increases as the oxidation time increases. The PL intensity and its peak wavelength are partially recovered by annealing the samples at 440K for 1h, suggesting the effect is metastable. It is proposed that the anomalous light-induced effect is originated from the defect states at the Si NCs∕SiO2 interfaces.

Microwave coupling of frequency-locked Josephson junction arrays

A high temperature superconducting YBa2Cu3Oy array of five Josephson junctions designed with additional coupling lines has been developed to demonstrate the effects of frequency locking and impedance matching for applications such as oscillators, mixers, and detectors. The Josephson self-radiation power was directly detected by a superheterodyne receiver, and Shapiro steps were also measured. The Josephson self-radiation properties reveal good quality of phase locking and microwave coupling with external circuits. The maximum self-radiation power of our array is about 50 pW which is several ten times higher than that of a single Josephson junction, and its peak point exactly satisfies the Josephson current-voltage relation. The Shapiro-step measurements show that the behavior of current-voltage curve depends on the effective inductance of coupling lines which affects the total impedance of Josephson junction array and microwave coupling. The Josephson oscillation frequency was obtained up to about 880 GHz...

Multibit memories using a structure of SiO2/partially oxidized amorphous Si∕HfO2

Memory capacitors with a structure of SiO2/partially oxidized amorphous Si (a-Si)/HfO2 have been prepared by sequential processes: atomic layer deposition (ALD) of 6nm a-Si on 3.5nm SiO2, thermal oxidation at 900°C, and another ALD of 12nm HfO2. The memory devices offer hybrid type of charge memory: the interface states of partially oxidized a-Si∕SiO2 tend to act as hole traps, resulting in a negative shift of flatband voltage in capacitance-voltage (C-V) curve, and the partially oxidized a-Si∕HfO2 interface has dominantly electron-trap centers, leading to a positive voltage shift. By this hybrid effect, the memory window in C-V curve is observed to be enlarged enough to realize four-level (2bit) memories, which is demonstrated through measurements of program/erase speeds and charge-loss rates.

Effect of hydrogenation on the memory properties of Si nanocrystals obtained by inductively coupled plasma chemical vapor deposition

Effect of hydrogenation on memory properties has been studied for metal-oxide-semiconductor (MOS) structures with Si nanocrystals fabricated using inductively coupled plasma chemical vapor deposition and subsequent annealing. Hydrogenation induces a drastic increase of a dip in the quasistatic capacitance-voltage (C-V) curve of the MOS capacitor, caused by the reduction of the interface states due to hydrogen passivation. This is consistent with high-frequency C-V measurements showing more well-defined curves with less distortion in hydrogenated samples. After hydrogenation, the MOS device shows a significantly larger decrease of flatband voltage shift in electron charging than in hole charging, indicating more effective passivation of the defect states related to the electron charging. A longer retention time is found for electron charging after hydrogenation, but almost no change of charge loss rate for hole charging. These results suggest that an asymmetry exists in the effect of hydrogenation between ...

Nonlithographic SiO2 Nanodot Arrays via Template Synthesis Approach

We present a method for fabricating SiO2 nanodot arrays through pattern transfer of self-organized tantalum oxide hard masks on to a Si wafer. Tantalum oxide nanopillar arrays are formed at the bottom of anodic aluminum oxide by electrochemical anodization of the Al/Ta films on a Si wafer. Then the tantalum oxide nanopillars were used as hard masks for formation of SiO2 nanostructures. Ion milling was used for the pattern transfer. The density and diameter of the SiO2 nanodot arrays could be controlled by varing the anodizing conditions. The average diameters and areal density of prepared SiO2 nanodisks were 68 nm and 1010/cm2, respectively. Through this approach, it is expected that a wide variety of nanodisk arrays over large areas can be prepared.

Characterization of Pd-nanocrystal-based nonvolatile memory devices

Charge loss rate of Pd-nanocrystal (NC)-based nonvolatile memories is reduced about 60% by employing an asymmetric tunnel barrier composed of stacked SiO₂ and HfO₂ layers or insulating ZrO₂ NCs between Pd NCs.

A New Operating Scheme by Switching the Polarity of Program/Erase Bias for Partially Oxidized Amorphous-Si-Based Charge-Trap Memory

In this brief, the authors propose a new program/erase (P/E) scheme for NAND-type partially oxidized amorphous-Si (a-Si)-based charge-trap memory in which the P/E voltages are interchanged into negative/positive ones, respectively. In the a-Si memory, the erasing speed was found to be faster than the programming speed, and therefore, the new scheme has been chosen to keep the program speed faster than the erase speed for the NAND operation. The P/E speeds in the new scheme increase at least ten times as those in the conventional P/E scheme. It is also shown that four-level memory states can be achieved via Fowler-Nordheim tunneling by applying programming voltage of -16, -18, and -20 V for each level during only 40 mus together with erasing voltage pulse (+20 V, 1 ms). These results indicate that the new P/E scheme is more effective than the conventional scheme for operating the partially oxidized a-Si-based memories